Impact of Layout on 90nm CMOS Process Parameter Fluctuations

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					                 Impact of Layout on 90nm CMOS Process Parameter Fluctuations
                                               Liang-Teck Pang, Borivoje Nikolic
                                                University of California, Berkeley, USA
                                 Abstract                                 Variations in stacked gates are less pronounced than those
   A test chip has been built to study the effects of layout on the   with single gates. Similarly, added poly stripes to maintain
   delay and leakage of digital circuits in 90nm CMOS. The            the uniform density reduce the variation effect as well.
   delay is characterized through the spread of ring oscillator       However the reduction in σ/µ of 0.3% is small, compared to a
   frequencies and the transistor leakage is measured by using        large reduction in average frequency of 11.5%.
   an on-chip ADC.                                                        Spatial correlation in variation is important to quantify, as
                               Introduction                           it could be exploited in statistical timing analysis. A weak
   Increased process parameter variation has been perceived as        spatial correlation is observed in the measurements, stronger
   one of the major roadblocks to further technology scaling.         in the horizontal than in the vertical direction (Fig.4). One
   The corner-based design approach treats all variations as          direction is along the slit of light and is subject to lens
   random. As the corner spread is increasing with technology         aberrations and curvature. The other is in the direction of
   scaling, simultaneously satisfying performance, power and          scan, which is subject to the variation in scan speeds and light
   yield requirements becomes challenging. In order to better         dosage. The layouts 6a/6b are rotated by 90o, and thus behave
   account for the variability in the design process, it is           differently than the others in Fig 4, confirming this trend.
   necessary to distinguish systematic shifts in parameter values          The variation in leakage currents exhibits the same trends
   from truly random ones. The variations are generally               as the RO frequency, but with larger relative values. WID
   characterized as within-die (WID), die-to-die (D2D) [1].           maximum layout-to-layout shift in average log(ILEAK) is ~20%
   While these relationships are generally known at the process       for single gates. Within-die within-layout σ/µ is 2-4%.
   level, they are hardly visible to the designer.                    Denser layout reduces leakage and tightens the spread. M1
                                Test Chip                             coverage over poly reduces leakage current to half its value
   The test chip, implemented in a general-purpose 90nm               and reduces the σ/µ by 1%.
   technology is used to evaluate the distributions of WID and            There is a strong positive correlation for log(ILEAK) vs
   D2D variations in ring oscillator frequencies and transistor       frequency spread only for D2D variation (mean of centers of
   standby leakage currents. The purpose of the experiment is to      patch) and between configurations (Fig.6). For the same WID
   evaluate the absolute magnitude of WID and D2D variations,         configuration, there is no visible correlation as given by a
   its spatial correlation, and the impact of layout styles. The      circular patch in the plot.
   chip contains an array of 10x16 tiles, occupying 1mm × 1mm                               Parameter Extraction
   area. Each tile has twelve 13-stage ring oscillators (ROs) and     Using the least squares method and the BSIM3 model, the
   12 transistors in the off-state, each with a different layout      variation in L and Tox can be de-embedded from the
   (Fig.1). The ring oscillators contain inverters with a single      frequency (F) and leakage current (I=log(ILeak) measurements
   poly finger, as well as a stack of three fingers. Poly density,    at varying Vdd (1.0, 1.4V), substrate bias (0V, -0.2V) and
   poly orientation and metal coverage are varied in the layout.      temperature (25oC and 60oC):
   To automate a large number of measurements, the RO                                          ∂F           ∂F 
   frequency is divided down and its value is scanned out of the                              
                                                                          F        L 
                                                                      Y =   , X =   , M =  ∂L          ∂Tox
   chip [2]. The tiles at the perimeter of the die are ignored in
                                                                          I       Tox       ∂I           ∂I 
   the measurements to eliminate edge effects. A single-slope                                                  
                                                                                               ∂L          ∂Tox
   ADC implemented using a high-gain folded-cascade
   amplifier with 2.5V devices, a large on-chip metal fringe          Fig.7 shows the de-embedded distribution of L and Tox
   capacitor and comparators was implemented on chip to               yielding a conclusion that most of the variation can be
                                                                      attributed to changes in L.
   measure transistor off-currents between 1nA to 1µA (Fig.2).
                                                                                                 Summary
                          Measurement Results                             Regular, layout reduces the systematic layout-dependent
   Measured data shows three dominant and distinctive trends          process variations, that are not captured by extraction. Since
   (Fig.3). The WID frequency variation for the same layout is        most of the variations are attributed to the channel length,
   small, up to 1.2% of the std. deviation/median (σ/µ). The          using high and uniform poly density reduces the random
   systematic median frequency spread over RO layouts with            variability, but at a large expense in average performance.
   different poly densities and orientations is much larger, up to    Since the spatial correlation is weak, design with larger logic
   11.5%. This spread is significantly larger than 1.1% predicted     depths can reduce the overall variability. Adjusting the
   by simulation of the extracted layout. Finally, the D2D            supply voltage and back bias can be used to effectively
   spread is large, from a typical to a fast simulation corner. The   compensate for D2D variations.
   ROs with single isolated poly fingers exceed the fast corner
   and are excluded from the measurements.




1-4244-0006-6/06/$20.00 (c) 2006 IEEE                                         2006 Symposium on VLSI Circuits Digest of Technical Papers
                       Acknowledgements                                                                                                       Horizontal                                                                        Vertical
                                                                                                                               1                                                                           1
      This work was supported in part by Marco C2S2. The
                                                                                                                            0.8                                        3a




                                                                                                 correlation coefficient
   authors thank STMicroelectronics for chip fabrication.                                                                                                                                                  0.5




                                                                                                                                                                                 correlation coefficient
                                                                                                                                                                       4a
                                                                                                                            0.6                                        5a
                                                                                                                                                                                                           0
                                       References                                                                           0.4
                                                                                                                            0.2                                                                            -0.5
   [1] J.W. Tschanz, et al, “Adaptive body bias for reducing impacts of die-to-
   die and within-die parameter variations on microprocessor frequency and                                                  1                        1b           4b                                            1
   leakage,” IEEE Journal of Solid-State Circuits, Nov. 2002.                                                               0.8                      2b           5b
   [2] D.Boning et al, "Test Structures for Delay Variability" TAU 2002.                                                    0.6                      3b           6b                                       0.5
   [3] M. Orshansky, et al. "Impact of spatial intrachip gate length variability on                                         0.4
                                                                                                                                                                                                           0
   the performance of high-speed digital circuits", IEEE Trans. CAD, May 2002                                               0.2
                                                                                                                            0 0           2     4    6    8      10 12 14                                  -0.50
                                   Dummy poly                                                                                                       Column
                                                                                                                                                                                                                      1     2
                                                                                                                                                                                                                             Row
                                                                                                                                                                                                                                   3    4    5   6     7
     1a M1 2a                      3a    4a                    5a           6a
                                                                                                 Fig.4 Plot of RO frequency spatial correlation coefficient between
                                                                                                 the 14 columns and between the 8 rows.
       1b           2b           3b             4b             5b                 6b
                                                                                                                                               NMOS Log(ILEAK) Distribution, 10 chips
                                                                                                                 40
                                                                                                                                    1a
                                                                                                                0
                                                                                                               40                   2a
                                                                                                                  0
                                                      ADC                                                        50                 3a
                                                                                                                  0
          1mm                                                                                                    40
                              Tile Array                                                                                            4a
                                                                                                                  0
                                                                                                                 40                 5a
                                                                                                                  0
                                                                                                                 50
                                                                                                                                     6a
                                                                                                                           0
     Fig.1 Layout configurations and die photo of the test-chip. Tile                                                               -20                   -18          -16                                          -14                -12
     pitch is 62.5µm horizontal and 100µm vertical.                                                                                                                                                                                    Log(ILEAK)
                                 VDD                                                             Fig.5 Plot of log(Ileak) distribution for ‘a’ configurations
                                                                                              Log(ILEAK)




     Leaky transistor
                                                          C
                            P1           P1                                 V1=1.8V
                                                                                                                           -15
                                                                                      stop
                                                                                 -
                              P2
                                                                                 +
                                                      -                                                               -17
                Gnd
                                                      +                          -    start                                                                                                                               O ‘3a’
                                         Iref                                    +                                    -19                                                                                                 + ‘4a’
                                                                     P1b
                  select                                                                                                                                                                                                  > ‘5a’
       Gnd                                      VDD                         V2=0.8V
                                   Gnd                                                                                     -21
                                                              0.7V
                                                                                                                                   7.5           8              8.5          9                                 9.5          10         Frequency

                                                                                                 Fig.6 Scatter plot of log(Ileak) vs frequency.
   Fig.2 Single slope ADC for current measurement.


                                                                                                                                              L distribution                                                              Tox distribution
                      RO Frequency Distribution, 10 chips                                                                  40                                                                               40
                                                                                                           3a                                                                                              3a
     3a 40                                                                                                                 20                                                                               20
         20                                                                                                                0                                                                                 0
          0                                                                                                                40                                                                               40
         40                                                                                                4a                                                                                              4a
    4a                                                                                                                     20                                                                               20
         20
                                                                                                                           0                                                                                  0
          0
                                                                                                                           40                                                                               40
         40                                                                                                5a                                                                                         5a
    5a                                                                                                                     20                                                                               20
         20                                                                                                                                                                  L                                                                             Tox
         0                                                                                                                  0 0.9                               1.0                                             0           0.8         1        1.2
               TT                                                      FF
                                   Frequency
   Fig.3 Frequency distribution for ‘a’ configurations. Vertical lines                           Fig.7 Distribution of normalized oxide thickness (Tox) and gate
   correspond to typical and fast corner simulation results.                                     length (L) for 3 layouts and 8 chips.




1-4244-0006-6/06/$20.00 (c) 2006 IEEE                                                                                                    2006 Symposium on VLSI Circuits Digest of Technical Papers