VHDL in an Introductory Digital Electronics Course
Daren R. Wilcox
Southern Polytechnic State University
1100 South Marietta Parkway
Marietta, Georgia 30060-2896, USA
Gerd W. Wöstenkühler
(University of Applied Studies and Research)
D-38855 Wernigerode, Germany
+49 3943 659-322
In this paper, a curriculum for an introductory digital electronics course using VHDL based on a custom
designed development board is presented. The development board is centered on the ispM4A CPLD.
The development of the CPLD teaching aid is the direct result of collaboration between engineering
faculty at Hochschule Harz (University of Applied Studies and Research) in Wernigerode, Germany and
Southern Polytechnic State University in Marietta, Georgia, USA. The discussion that follows includes
an overview of VHDL in engineering education, an overview of the ispM4A, a design review of the
teaching aid, and a discussion of how it can be used in an introductory digital electronics course.
Steven J. Hanke of Texas Instruments marketing wrote in the EETIMES, “Experts have been
proclaiming the imminent demise of discrete logic just about as often as prognosticators have predicted
the end of the world. We’re still here, and all signs point to a vital role for discrete logic in the years
ahead.”  That was written in December of 1998. It is now October of 2007. Barring any unknown
rapture, the world is still here and discrete logic is still with us. However, its existence has undergone a
digital Darwinism to evade extinction . Today, discrete logic is used as a means to “glue” more
complex programmable logic devices (CPLDs) together. One complex programmable logic device and
small amount of VHLD code can literally replace hundreds of discrete logic components. The cost
advantage held by discrete logic devices for the last several decades has evaporated. The advantages
CPLDs have are in production costs, board area savings, operating performance, reliability, time to
market, programmability, electromagnetic interference, and design security . Over the last decade,
the rapid acceleration of adopting CPLDs has left a pedagogical mess.
The typical engineering and engineering technology fundamental digital electronics course, up until
recently, has reflected the history of digital design. Originally, digital designs were implemented with
small scale integrated (SSI) devices such as the 7400 series TTL chips introduced in 1962 which became
widely available in 1968 . The design would be derived from Boolean expressions usually in the
sum-of-products form. The product represents the AND operation and the sum represents the OR
operation. The sum-of-product logic is the educational standard realization for so called combinational
logic. To implement sequential operations such as a state machine, the result of the sum-of-product
expression would be stored into a clocked memory element such as a flip-flop. During the clock period,
the memory element holds the present output of the state machine allowing for the output to be routed
back to the sum-of-product logic thereby determining the next state that will result on the next clock
pulse. Using a memory element such as the flip-flop to store the output of the combinational logic is
often referred to as registered logic.
Combinational logic and registers are so common in fundamental digital systems that combining the two
onto a single chip was a natural step. The results of the combination are programmable array logic
(PAL) devices and generic array logic (GAL) devices. In PAL devices the product terms are
programmable and feed into a fixed OR gate array. Additional logic is available including registers.
GAL devices are very similar to PAL devices but have reprogrammable AND arrays and more extensive
logic. The PAL was a development of Monolithic Memories, Inc. in 1978 . The GAL was a
development of Lattice Semiconductor Corporation circa 1987. Since then, as more complex devices
have been introduced the first PAL and GAL devices have been referred to as simple programmable
logic devices (SPLD).
The same progression outlined above has been reflected in the typical course sequence of fundamental
digital electronic courses. The course starts out with an introduction to digital concepts such as the
difference between analog circuits and digital circuits. Next binary numbering systems are introduced.
Then basic logic operations such as the NOT, AND, OR, NAND, and NOR are presented followed by
7400 series TTL gate realizations. The 7400 series of TTL gates are referred to as SSI devices. Next in
the sequence is deriving sum-of-products expressions from truth tables. The sum-of-products
expressions are then reduced using Boolean algebra followed by the use of Karnaugh maps. The SSI
section is concluded with same series gate realizations of sum-of-product expressions such as a two
level NAND-NAND realization of a sum-of-products expression. The combinational logic sequence
concludes with medium scale integrated (MSI) realizations of more advanced logic functions such as
comparators, decoders, and multiplexers to name a few.
The course sequence then typically introduces the registered logic of latches and flip-flops. Counters
and state machines that employ the sum-of-products logic along with flip-flops follow next.
Considerable time is allocated to counter and state machine design because of the complexity of the
system. Both SSI and MSI chips are used. The logic sequence is usually concluded with shift registers.
The PAL devices are usually introduced after the conclusion of the combinational logic sequence. The
GAL devices are usually introduced at the conclusion of the registered logic sequence. Until around
2003, the PAL and GAL devices were programmed using either the CUPL or ABEL hardware
description languages. Therefore, each language was introduced within the PAL and GAL sections.
Today’s pedagogical mess is a direct result of CPLDs becoming more economical and relegating
discrete logic to ancillary functions. Every SSI and MSI function can be implemented with a CPLD
using simple VHDL code. So if VHDL and CPLDs can replace virtually all of the discrete logic to the
point where the logic devices are block diagrams on schematic capture software, what learning
experience must be retained from the now defunct discrete logic courses? The answer is electrical
characteristics, interfacing, system design, and system troubleshooting. The next question is how should
VHDL be taught using CPLDs in a student friendly way while retaining the discrete learning experience.
In this paper, a low cost development board is presented based on the Lattice Semiconductor ispMach
series of CPLD. The board is intended to replace the 7400 TTL series and GAL series learning
experience with a more complex chip yet retain the same educational experience of learning interfacing
and trouble shooting skills. Also presented is a suggested course sequence using the ispMach
2. Overview of ispM4A5 CPLD
2.1 ispMACH Series
The ispMACH 4A complex programmable logic device (CPLD) family was introduced in 2000 as the
first product family of the unified corporation composed of Lattice Semiconductor and Vantis, a spin off
of AMD . Consistently over the past few years, Lattice reports that PLD products account for more
than 82% of their annual revenue . The ispMACH 4A series offers devices that contain from 2 to 32
PAL blocks. Each PAL block contains 16 macrocells which are composed of registered logic and
routing elements. The PAL block is similar to the function of the PAL and GAL chips previously
mentioned. The ispMACH 4A series also offers mixed voltage support with 3.3-Volt and 5-Volt which
allows interfacing to older TTL technology.
2.2 ispM4A5 64/32
The educational development board presented in this paper is designed around the ispM4A5 64/32 44
pin PLCC device. The block diagram for the chip is shown in Figure 1. The ispM4A5 has four PAL
blocks labeled A, B, C, and D. This is roughly equivalent to having four of the 1978 era PAL devices
on one chip. The PAL blocks are interconnected by the central switch matrix shown in the center of the
In each PAL block, the AND logic array connects to the central switch matrix. The AND logic array is
the first level of the sum-of-product expression. The AND array feeds into the OR array contained in
the logic allocator block which completes the sum-of-products expression.
Each PAL block has 16 registers available. The registers are located in blocks referred to as macrocells.
Each macrocell contains a register, routing resources, a clock multiplexer, and initialization control.
Figure 2 shows the macrocell configured in the synchronous mode. The register can be configured as a
D-type or T-type flip-flop. The register can also emulate J-K and S-R flip-flop behavior .
Figure 1. ispM4A5 64/32 Block Diagram 
3. Design Review
The ispM4A5 lab board is shown in Figure 3. The design is focused on students who are beginners in
the area of programmable logic devices. The sophisticated complex designs make it hard to get started.
Therefore a comparable robust design with clear and simple structure is used and, just in case, all ICs are
in a socket and all parts are through whole components for easy repair.
Figure 2. Macrocell Block Diagram 
Located in the center is the Lattice ispM4A5 64/32, 44 pin PLCC CPLD. Directly above is the JTAG
connector used to program the chip while it is in the system, hence in system programmable (isp).
Above and to the left are a USB connector and a screw terminal connector. Either connector can be
used to provide the board with a supply voltage. By having the USB connector, the board can be used in
the academic laboratory without the need for an expensive power supply. The board can be powered
from any computer with a USB port. Below the power connectors is the clock generator chip, namely
the 74HC4060N. The jumper connectors are used to select clock frequencies of 2, 8, 32, 128, 512, 1024
and 2048 Hz (the second clock input of the CPLD gets a 4 Hz clock signal). Along the bottom are four
switches and four pushbutton inputs. On the bottom and in the center are four seven segment displays.
The four switches with the buttons and the seven segment displays from left to right are connected to the
blocks A to D of the CPLD. Pins A7..A0, B0..B7, C7..C0, and D0..D7 of each respective block are used
as outputs for the segments a to g and the dot of each seven segment display. The eighth signal that is
connected to the dot is also connected to the switch with parallel pushbutton. The eighth signal can be
used as an input. Above the seven segment displays are two vertical rows of colored LEDs. The signals
of Block A can be switched to these LEDs. Above the LEDs and also to the right are banks of resistor
packs used as the current limiting resistors for the LEDs. Based on the TTL logic level and the 5V
power supply the LEDs are on when the signal is LOW. Furthermore, the pushbutton and switch inputs
are active LOW also. Finally, on the right side of the board are two 20 pin sockets.
Figure 3. ispM4A5 lab board
The two sockets located on the right of the board allow for two 20 pin flat ribbon cables to be connected
to the ispM4A5 board on one end and the other end can serve as a 20 pin DIP surrogate. The male end
of the cable can be connected to a student’s breadboard.
4. Course Organization
In traditional logic courses, the main learning experience gained from discrete logic is an understanding
of electrical characteristics, interfacing, system design, and system troubleshooting. The student is able
to easily associate the simple logic function to the discrete gate. For example, the NOT function is
easily associated to the inverter gate of the TTL 7404 where pin 1 is the input and pin 2 is the output.
The electrical characteristics are learned, for example, by discriminating the differences of the standard
7404 to the low power Schottky 74LS04. The interfacing is learned by driving one discrete series with
another such as a 74LS04 into a 74HC04 or by displaying logic levels using LEDs. A simple state
machine design forces the student to interconnect several SSI and MSI discrete gates, which to a student,
represents a significant system design process. In the process, students destroy individual gates and
misconnect sub-circuits which present excellent opportunities to learn troubleshooting skills. When
employing a single CPLD, most of this experience is lost because all the logic will fit on a single CPLD.
At Southern Polytechnic State University, the present compromise is to attempt to identify core discrete
gates that will continue to be used as “glue” logic and introduce those first in the introductory digital
electronics course. For example, the first laboratory exercise is to investigate the properties of the
74LS04 Hex Inverter, the 74LS08 Quadruple 2-Input AND Gates IC, and the 74LS32 Quadruple 2-Input
OR Gates IC. The 74LS04 is a simple discrete chip that can be connected to a load resistor and LED to
verify the TTL datasheet electrical characteristics. Characteristics such a VOH, VOL, VIH, and VIL are
easily demonstrated using the 74LS04. The logic function of the 74LS08 and 74LS32 can be easily
The second laboratory exercise again uses the 74LS04, 74LS08, and 74LS32. In this lab, logic function,
interfacing, and troubleshooting are taught. The 74LS08 driving the 74LS04 yields the NAND logic
function. The 74LS04 driving the 74LS08 can yield the NOR logic function. The 74LS04 driving the
74LS32 can again yield the NAND logic function. If any of the gates are bad or the student places a
wire on the wrong pin, the student will learn how to troubleshoot the problem.
The third laboratory exercise uses the 74LS04, 74LS08, 74LS32, and the 74LS00 Quadruple 2-Input
Positive NAND Gates IC. The majority of this lab is used to investigate the universal properties of the
NAND gate. A complex sum-of-products expression is first implemented with the ’04, ’08 and ’32. The
same expression is then again implemented with only the 74LS00 gates.
At the completion of the first three laboratory exercises, the student should have a good conceptual idea
of the function of individual logic gates and be aware of how to interface the devices along with
troubleshooting should the circuit not function properly. The fourth and fifth laboratory exercises use
the 74LS00 and the 74LS20 Dual 4-Input Positive NAND Gates ICs to further reinforce the sum-of-
products realization before and after logic reduction, first using Boolean algebra then using Karnaugh
By the sixth laboratory exercise, the course material has reached the MSI level of discrete logic. The
course material is beginning to discuss adders, comparators, decoders, encoders, multiplexers, etc. Now
is when the CPLD can be introduced to implement these devices. For example, a simple yet impressive
sixth laboratory exercise uses the CPLD to decode a binary input for output on a seven segment display.
The CPLD and seven segment display are included on the ispM4A5 development board. The VHDL
code can be written in a structural form where logic equations are expressly written for each segment a
through g of the seven segment display. In this lab, student’s attention is moved away from the
electrical characteristics and interfacing back towards the development of logic.
Through experience, it was noted that even by the seventh laboratory, students were not quite ready to
abandon discrete logic all together. The seventh laboratory exercise was designed to include SSI, MSI,
and CPLD logic devices. The students were required to design a simple multiplexer with only 74LS00
NAND gates. Then apply the 74LS157 Quadruple 2-Line to 1-Line Data Selector/ Multiplexer IC in the
same fashion. The third exercise was to design the same multiplexer in VHDL using the ispM4A5
development board. Realizing the same logic with all three device technologies pulled the material
together for the students.
The remaining laboratory assignments are centered on using VHDL to realize an equivalent
implementation of discrete MSI logic on the CPLD development board. Decoders, shift registers,
counters, and state machines are taught in VHDL using a structural, data flow, or behavioral approach.
The board can be used for different realizations of state machines like a traffic light sequencer or a
vending machine controller. The implementations include sectional test of the (sub-) modules in the real
world and discussions of used hardware (e.g. number of used macrocells).
As a final consideration, a project that pulls all the key learning experiences together is implementing a
basic traffic light sequencer using VHDL. The ispM4A5 development board can incorporate all aspects
of such a design. The board has the necessary inputs and outputs. The CPLD is more than capable to
handle the VHDL code. The size of the VHDL code requires the students to learn system design. Since
the project can fit entirely on the board, the students’ learning experience of interfacing and trouble
shooting is limited. However, additional circuits can be interconnected to the board using a 20 pin
The introduction of VHDL in a fundamental digital electronics course presents challenges to course
development. The main learning experiences that should be retained from earlier discrete courses is
interfacing and troubleshooting. The logical point of VHDL inclusion in the course sequence is at the
time when MSI devices such as multiplexers, decoders, etc. are introduced in lecture. This is usually
after Boolen algebra and Karnaugh map reduction. However, instead of using the MSI device, the
CPLD is used in its place.
The educational laboratory board presented in this paper allows educators to begin the transition into
teaching VHDL designed digital circuits while retaining the fundamental student learning experience of
interfacing and troubleshooting digital electronic circuits. The board allows for simple emulation of
discrete logic by interconnecting the board to student built circuits via a 20 pin ribbon cable. As the
digital course material advances, the board can be used as a self-contained experiment station.
The authors would like to thank Dan Pratt of Lattice Semiconductors for generous support of laboratory
equipment and software for Southern Polytechnic and Hochschule Harz. The authors would also like to
thank AusThai Solutions for their assistance in fabrication.
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 Dipert, Brian. “Digital Darwinism: Discrete Logic Evolves to Evade Extinction”, EDN, 20
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Paper: CPLD, WP202 (v1.3), 10 January 2005
 Advanced Micro Devices, Inc. PAL Device Data Book: Bipolar and CMOS, Sunnyvale: 1990
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3.3- and 5-Volt CPLDs; New Family Provides High Performance, Lower Power, Lowest Price –
Product Announcement”, 10 April 2000,
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http://www.latticesemiconductor.com/corporate/about/productprofile.cfm, (26 Feb. 2007)
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System Programmable Logic”, ISPM4A Data Sheet, 2006,