"Ali Namazi E mail ali namazi student utdallas edu Mobile"
Ali Namazi E-mail: email@example.com Mobile: (972) 213-8143 Address: 2200 Waterview Parkway, Apt. 31202, Richardson, TX 75080 Objective To obtain a summer internship/Co-op position in the Computer engineering area, especially in hardware design and development programs. I’m also interested in full-time jobs with H1 sponsorship. Education PhD in Computer Engineering, UT Dallas (Expected Graduation August 2009) GPA: 4.0 Topic: Nanoelectronics Courses: VLSI + Hardware Testing MSc in Digital Electronics, Sharif Univ of Tech, Tehran, Iran (Graduation January 2000) GPA: 3.2 Topic: HQ Audio Compression with DSP BSc in Electronic Engineering, Sharif Univ of Tech, Tehran, Iran (Graduation August 1997) GPA: 3.0 Topic: Design and Development of Data Logger System Professional Skills VHDL/Verilog Programming and FPGAs, Very High-Speed Logic Design, DSP (Audio Signals), Protocols (PCI-Express, PCIX, PCI, USB), Embedded Programming (C++) Industry Work Experience Senior Hardware Engineer Nixo Co., Tehran, IRAN 8/2005 – 4/2001 Designed and developed a PCI-Express protocol analyzer/exerciser. This product is an intelligent bus monitoring and device emulation system, which helps PCI-Express system developers on debugging their products throughout their development process. PCI-Express is the Third Generation IO of CPUs after ISA and PCI recently introduced by Intel. Worked as the leader of a group of talented HW engineers and the designer of the system. Some features of this product are: o Up to 16 lane analyzer/exerciser at 2.5Gbps per lane o 2.5 Gig-Byte on-board memory (DRAM) o Ability to capture any desired packet and trigger on complex sequences of packets or events o 250MHz working frequency of the logic implemented on a VirtexII-Pro Xilinx FPGA Designed all of its functional blocks and also the schematic capture and PCB. Implemented some of its critical modules such as the serial to parallel controller logic (with clock correction and multi- lane channel bonding blocks) and the SDRAM controller logic. This HW design is re-usable for other protocols too. Now it’s ported to Serial ATA (SATA) and Serial SCSI (SAS) protocols and new products are expected to be released soon. Hardware Engineer Ganjineh Co., Tehran, IRAN 3/2001 – 1/2000 Developed an RSA cipher/decipher hardware that is used in an HF modem system. The algorithm was based on a 16-bit modular cascade-able design with a high restriction on the low logic usage and area optimization. Attached 8 of them to create a 128-bit RSA cipher system and tested it on the board. In addition, developed two other algorithms (IDEA and 3-DES) on this board. Hardware Engineer Nixo Co., Tehran, IRAN 12/1999 – 4/1998 Worked on a PCI and PCIX bus analyzers and exercisers in a HW team. Developed a “Protocol Violation Detector” logic which inspects bus transactions and finds out all possible protocol violations performed by bus agents and devices. Responsible of developing some minor modules and test and verification of the entire system during training period. Academic Experince • Research Assistant at UTD: Working on the reliability issues of the future nano-chips components and interconnects, and related testing methods from system level viewpoint. • Developed a new speech spectral envelope estimation model using weighted Linear Prediction coefficients for better compression rate while keeping voice quality during MS. • Presented workshop on Spread Spectrum and CDMA techniques. Languages Persian (maternal language), English (fluent), Italian (second maternal language).