Lab Exercise #3

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					                    CCE 3202 – Advanced Digital System Design

Lab Exercise #2


Introduction


You will use Xilinx Webpack v9.1 to allow the synthesis and creation of VHDL-
based designs. This lab will outline the steps necessary to synthesize, download, and
test a 1-bit, two function ALU, with the following schematic and truth table:




Truth Table:

F0        Function
0         Q0 = A0 OR B0
1         Q0, COUT = A + B




Deliverables for Lab Exercise #2

When completed, you will hand in the following deliverables for Lab Exercise #2, in
this order:


           1.   Title Page
           2.   Commented VHDL sourcecode
           3.   Simulation waveforms verifying your ALU's operation
           4.   Summary report of your results, problems encountered, etc.
All synthesis tools use files called "netlists." Netlists are simply text descriptions of
how various circuit components are connected. The HDL design flow is similar to
Schematic Capture, except that it deals with VHDL code instead of schematic
drawings. Xilinx ISE can take VHDL and create a netlist based on your code.

Here is the VHDL code that we will use to implement this circuit:
        library IEEE;
        use IEEE.std_logic_1164.all;

       -- A 1-bit, two function ALU
       -- alu_test.vhd
       entity alu_test is
          port (
             A0: in STD_LOGIC;
             B0: in STD_LOGIC;
             F0: in STD_LOGIC;
             Q0: out STD_LOGIC;
             COUT: out STD_LOGIC
          );
       end alu_test;
       architecture alu_test of alu_test is
         signal CIN: STD_LOGIC;

         begin

          CIN <= '0';
          process (A0, B0, F0)

          begin

            if F0 = '1' then

              Q0 <= A0 xor B0 xor Cin;
              COUT <= (A0 and B0) or (A0 and Cin) or (B0 and Cin);

            elsif F0 = '0' then

              Q0 <= A0 or B0;
              COUT <= '0';

            end if;

          end process;

       end alu_test;

As you can see, this code uses a single process to implement the circuit. You may be
wondering why we used a process instead of structural VHDL statements. Well, there
are two reasons. First, when you want to use "if" statements in VHDL code, it is
generally best to use such statements inside a process. This is because "if" statements
used outside of processes infer the use "generate" statements, and this is something
we want to avoid because they unnecessarily complicate the code. In addition, one of
the purposes of this assignment is to use behavioral VHDL code instead of structural
VHDL. When we use such "if" statements, that is, "if this input satisfies this
condition, then do this," we are actually writing a behavioral description of how the
circuit should operate as opposed to a "connect A to B"-type description.
Notice that the sensitivity list contains all of our inputs. When any one of our inputs
change, we want this process to execute because it will have an affect on our outputs.
The compiler will look at this code and automatically realize that we aren't using any
clock-based logic, and will implement this code as a simple combinatorial circuit (no
flip flops).
Finally, notice how the code implements the ADD function. We simply take the
equations for an adder and implement them in a single statement. A full adder's
"SUM" output is simply "A xor B xor Carry_In", and a full adder's "Carry_Out"
output is simply "(A and B) or (A and Carry_In) or (B and Carry_In)." We take these
equations and set the outputs accordingly. We created a signal called "Carry_In" and
set it to zero for convenience.

 The output of the ALU will be output on the 7 segment display. The VHDL code for
the 3 – 7 decoder circuit is written according to the following truth table.

Q0                    COUT                  F0                    Display
0                     0                     0                     0
0                     0                     1                     2
0                     1                     1                     3
1                     0                     0                     1
1                     0                     1                     4
1                     1                     1                     5
library IEEE;
use IEEE.std_logic_1164.all;

entity DEC_7seg is
        port (
                  Din: in STD_LOGIC_VECTOR (2 downto 0);
                  Segments: out STD_LOGIC_VECTOR (6 downto 0)
               );
end DEC_7seg;

architecture DEC_7seg_arch of DEC_7seg is
--
--      ------(6)------
--      |              |
--     (1)            (5)
--      |              |
--      ------(0)-------
--      |              |
--     (2)            (4)
--      |              |
--      -------(3)------

       begin
          process(Din)
          begin
              case Din is
                     when "000" => Segments <= "0000001";
                     when "001" => Segments <= "0010010";
                     when "011" => Segments <= "0000110";
                     when "100" => Segments <= "1001111";
                     when "101" => Segments <= "1001100";
                     when "111" => Segments <= "0100100";
                     when others => Segments <= "1111111";
              end case;
           end process;

end DEC_7seg_arch;
The top level Code is:

library IEEE;
use IEEE.std_logic_1164.all;

-- An ALU

entity alu_top is
   port (
      INA: in STD_LOGIC;
                  INB: in STD_LOGIC;
                  INF: in STD_LOGIC;
                  Q: out STD_LOGIC_VECTOR (6 downto 0)
   );
end alu_top;
architecture alu_top of alu_top is
    component alu_test -- component declaration for the T-Flip Flop
     port (
       A0: in STD_LOGIC;
       B0: in STD_LOGIC;
       F0: in STD_LOGIC;
       Q0: out STD_LOGIC;
       COUT: out STD_LOGIC
                         );
    end component;

   component DEC_7seg -- component declaration for 7 segment decoder
   port (
                Din: in STD_LOGIC_VECTOR (2 downto 0);
                Segments: out STD_LOGIC_VECTOR (6 downto 0)
             );
          end component;
  signal S0, S1: STD_LOGIC; -- various intermediate signals
  signal G: STD_LOGIC_VECTOR (2 downto 0);

   begin

     ALU1: alu_test port map (INA,INB,INF,S0,S1);

       G(0) <= INF;
       G(1) <= S1;
       G(2) <= S0;

          --Now initiate the 7-segment display
     DISPLAY: DEC_7seg port map (G, Q);


end alu_top;
Simulation

You can now simulate the circuit in the same way that we have done last time.

Synthesizing the VHDL with Xilinx ISE

You are now ready to check the syntax of the code and to synthesize it as well. Open
the Synthesize XST tree within the process dialog box and run "Check Syntax".
Notice the output of this operation in the window at the bottom of the HDL editor.

If for some reason your file has an error in it, a red x would appear next to file in
place of the green check. If this happens, right click on the filename and click on
"Edit" to fix the problem.

Now we have to synthesise the circuit. First we need to define the pins that will be
used. In the sources dialog box select Synthesis/Implementation. In the process dialog
box open the tree of the Implement Design and then Translate. Select the Assign
Package Pins Post-Translate, right click and “Run”. This will open the PACE utility.
Enter the locations of the pins:

       NET INA LOC P6;
       NET INB LOC P10;
       NET INF LOC P12;
       NET Q(0) LOC P83;
       NET Q(1) LOC P17;
       NET Q(2) LOC P20;
       NET Q(3) LOC P21;
       NET Q(4) LOC P23;
       NET Q(5) LOC P16;
       NET Q(6) LOC P25;

These statements mean are telling the synthesizer where to place the inputs and
outputs. Save your work.

You can now run the Synthesis and Implementation. Select Synthesize in the process
dialog box, click the right mouse button and select “Run”. Then select Implement
Design in the process dialog box, click the right mouse button and select “Run”. This
will translate the design, map it on to the FPGA, select the slices to be used and do the
routing. Finally select the Generate Programming File in the process dialog box, click
the right mouse button and select “Run”. This will generate the .bit file required by
the FPGA.

Downloading and Testing

Now all that's left is to find the alu_top.bit file that was generated, and download it to
the BASYS board (using the same procedure as in last lab).

				
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