# Computer Arithmetic 2 - École dingénierie et de technologie de l

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```					CEG2131: Computer Architecture I
(MI) 5/1/2010

Lecture 5: Arithmetic: Multiplication/Division
Basic Multiplication:

We have to multiply A and B (unsigned or signed).
A = a n-1, a n-2 , … a 2, a 1 , a 0
B = b n-1, b n-2 , … b 2, b 1 , b 0

Result = A * B. Here A is called the Multiplicand MPCND and B the
Multiplier MPLR.

In the unsigned case the result may occupy 2n bits. For the signed
case the result can be at most 2n-1 bits long since we have to reserve
one bit for the sign itself.

We have to understand the process of long multiplication before we
can look at the architecture.

Long Multiplication:

25 * 21 = 525,
Two 5 bit registers MPCND = 11001, MPLR = 10101 will result in a
product Register that can be 10 bits long.

LONG MULTIPLICATION
1   1 0 0 1 MPCND
1   0 1 0 1 MPLR
1   1 0 0 1 Form Partial Product
PP0 = MPCND * MPLR0 , b0 = 1
0 0   0 0 0     Shift Left MPCND,
PP1 = MPCND * MPLR1 , b1 = 0
1 1 0     0 1       Shift Left MPCND,
PP2 = MPCND * MPLR2 , b2 = 1
0 0 0 0       0         Shift Left MPCND,
PP3 = MPCND * MPLR3 , b3 = 0
1 1 0 0 1                   Shift Left MPCND,
PP4 = MPCND * MPLR4 , b4 = 1
1 0 0 0 0 0           1 1 0 1 ADD all PPs
Result = 512 + 13 = 525

If the MPCND is negative, propagate the sign bit (1) to all the MSB
positions of the MPCND register.
Example: see book
Registers Needed for Unsigned Multiplier

B: MPCND Register

Control Logic
Comple                       BitC
menter

C       A: ACCUMULATOR           Q: MPLR Register

Multiplication Algorithm:

1. C  0, A  0, Q  MPLR, B  MBCND, BitC  # of bits
2. Examine the lowest bit of Q Regsiter,
If 1 then A  A add MPCND
3. Considering C, A and Q as a unit, Shift right by 1 position,
discard the right most bit of Q.
4. Decrease Bit Counter, BitC  BitC – 1
5. If BitC > 0 goto step 2
6. The Product is in CAQ
For the unsigned Divider we need a similar structure , but the usage
is different.

   B contains the divisor, DVSR
   A and Q contain the dividend DVDND
   Shifts of CAQ are performed to the Left instead of the right
   The result Quotient QUOT is in Q and the remainder RMNDR is
in A

Divisor Algorithm:

1. A  Rest of DVDND , Q  DVND Lower part,
B  DVSR, BitC  # of bits
For i = 0 to (BitC – 1) do steps 2 to 3
2. Shift Left AQ as a unit
3. If DVDND >= DVSR, A >= B then,
Qi = 1, and A  A – B
Else Qi= 0
4. The Quotient QUOT is in Q and the remainder RMNDR in A
Fast Multiplication Method:

Booth Multiplier:

Is based on a different interpretation of binary number encoding.

Conventional interpretation: 111 = 1* 2 2 + 1* 2 1 + 1* 2 0 = 4 + 2 + 1 = 7

Booth’s Interpretation:

111           =23–20 =7
111100        = 2 7 – 2 2 = 124

                    = 2 (e + 1) – 2 b

where e is the end position of a string of 1’s and b is its begin
position.
01110       = 2 4 – 2 1 = 14

In the same manner we can express 110111 as

(2 6 – 2 4 )+ (2 3 – 2 0 ) = (64 – 16) + (8 – 1) = 48 + 7 = 55

If we can express the Multiplier by partitioning its string of 1s in
Booth’s form then the process of multiplication can be simplified to

Booth’s Multiplier Encoding Algorithm:

1. Append a zero to the lowest bit position of the multiplier.
Call it Q(-1)
2. Scan the Multiplier from Left to Right.
3. For i = 0 to n -1
Examine Q(i) and Q(i-1)
= 00 or 11  encoding = 0
= 01          encoding = + 1
= 10          encoding = - 1

Example: Encode 0 1 0 1 1 1 0
+1 -1 +1 0 0 -1 0
Booth’s Multiplication Algorithm:

1. Initialize:
C  0, BitC  Num of Bits ,
A  MPCND (sign extend 1’s if negative),
Q  MPLR, ENQ  Booth Encoded MPLR

2. Scan ENQ Register from Right to Left:
For i = 0 to ( n – 1)
Algebraic Shift ACQ (as a whole) Right by i.
If ENQ i = – 1, then subtract original Q from A:
A  A + Q’ + 1 (2’s complement of Q)
If ENQ i = – 0 do nothing
If ENQ i = + 1 then add original Q to A:
AA+Q

3. The result is in Regs A and Q.

Example:
Modified Booth’s Encoding:

The conventional Booth’s encoding involving subtraction of Q from
the shifted CAQ registers. We want to avoid a situation where there
are a large number of subtractions such as in the case of an encoded
multiplier e.g. +1 -1 +1 -1 ..

In such cases it is possible to rescan the encoding in bit-pairs and
examine their net effect on multiplication. Thus +1 -1 can be regarded
as +2 1 – 2 0 = +2 – 1 = 1, i.e. multiplication by 1.

Recode the bit-pairs of the encoded multiplier as follows:
Booth’s   Evaluation       Modified Multiplier’s Remarks
Encoding                    Bit-Pair Original Bits
i + 1, i                   Encoding i + 1, i, i – 1
0 0      0*2 1 + 0* 2 0        0     000 or 111
1        0
0 +1     0*2 + 1* 2           +1         001
0 -1     0*2 1 - 1* 2 0       -1         110
1        0
+1 0      1*2 + 0* 2           +2         011
1        0
+1 +1     1*2 + 1* 2           ---         ---       Can be merged
+1 - 1    1*2 1 - 1* 2 0       +1         010
-1 0      -1*2 1 + 0* 2 0      -2         100
- 1 +1    -1*2 1 + 1* 2 0      -1         101
1        0
- 1 -1    0*2 + 0* 2           ---         ---       Can be merged

Thus Booth’s original encoding of +1 -1 +1 -1 +1 -1 can be recoded as
+1 +1 +1

Example Modified Bit-Pair encoding:
Let the Multiplier Q be +21 = 010101 and the multiplicand be + 13.

0 0 1 1 0 1                 Multiplicand = 13
0 1 0 1 0 1                 Multiplier = 21
+1 -1 +1 -1 +1 -1           Initial Booth’s encoding
+1    +1    +1            Modified Bit-pair encoding
0 0 1 1 0 1                 13 * (+1)
1 1 0 1 0 0                 13 * (+1) * 4
1 1 0 1 0 0 0 0                 13 * (+1) * 16
0 1 0 0 0 1 0 0 0 1                 PRODUCT = 256 + 17 = 273
Registers Needed for Unsigned Division:

B: Divisor Register

Subtract    Control Logic
Comple                               BitC
menter
Shift
Left

A: ACCUMULATOR                  Q: DVDND Register

Multiplication Algorithm:

1. Initialize:
A  DVDND, Q  DVDND, B  DVSR, BitC  # of bits
2. Shift Left AQ
3. A  A – DVSR (trial subtraction)
If A is Positive then set Q0 = 1
Else restore A to its previous value by
A  A + DVSR, also Set Q0 = 0
4. Decrease Bit Counter, BitC  BitC – 1
5. If BitC > 0 goto step 2
6. The Quotient is in Reg Q , the remainder is in Reg A.

Example:

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