13210 Uvas Rd. Morgan Hill, CA 95037
Phone: 480 510 5193
Senior Field Applications Engineer
EDA Design and Verification Tools
QUALIFICATIONS • MSc in Microelectronics Systems Design with 20 years of design experience
providing a solid foundation in EDA design and verification tools
• Sales-Driven technical field resource trained in strategic account development.
• Professionally trained to provide high-level presentations
Cadence Design Systems 2002 – To date
Principal Product Validation Engineer – Analog Mixed Signal
Responsible for managing the regression tests for Cadence's Analog Mixed Signal/Language simulator (AMS) along
with personal and customer PCR's.
• Manger of the Analog Platform Flow Methodology test suite for flow testing AMS, Assura, Spectre, Aptivia,
• Active in the AMS product and test specification reviews.
• Created a regression test suite for the Custom Netlister and hierarchical bus functionality, the tests comprised
Makefiles and Skill routines.
• Manager of the Xrunner GUI testing software for AMS, responsible for maintaining, and updating the
Innoveda Inc. (formerly Summit Design and Viewlogic) 1997 to 2002
Senior FAE - SOC Design/Verification Tools
• Worked in both San Jose and Phoenix with major companies such as Cisco, Sun, SGI, Motorola & Intel
alongside many start-ups.
• Established excellent customer relationships through exemplary service.
• Focused on the System Design and Verification tools for C++, SystemC, VHDL and Verilog
• Responsible for presentations, demonstrations, and evaluations.
• Refined demonstration databases and produced training material.
• Team player – mentoring FAE’s along with pre-sales support in other territories
Primary engineer involved in the companies major $1MM term deals- SUN and Motorola.
Presidents club 2000
Presidents club 2002 – top over quota AE in the US (160%)
Instigated and organized many “Lunch and Learn” seminars to help grow business.
Generated a code coverage methodology flow and presented throughout the USA, this was also distributed to
the FAE’s as its purpose was to increase product usage.
Created an evaluation criteria document to help the sales force promote the benefits of the tools and focus on
an efficient methodology
Instigated and organized 2 seminars for all client companies in the Phoenix area
GEC Plessey (Lincoln/Oldham) 1992 to 1997
• Member of the Network group producing 10/100 BaseT transceivers
• Member of the Mass Storage ASIC group working on hard drive and magneto optical controllers.
• The designs were created using Cadence Schematic Capture, Layout, Verilog, Spice and Synopsys Design
Design of data interface, floor-planning and physical layout of output driver amplifiers.
Designed an optimized FIR filter and presented a technical paper at ITC’95
Managed the design of several chip variants.
AMDET, SMDET and 2,7 RLL decoder design in differential logic.
Pyramid Consultants (Continued) 1990 to 1992
• ASIC design consultancy, producing and presenting training courses
Cadence Design Systems 1989 to 1990
ASIC CAD Consultant
• Product specialist for Cadence’s technology leading array routing software (TANGATE)
• Stimulated considerable interest for Cadence at trade shows throughout Europe.
• Product training in Scandinavia and Germany
Technical Sales Lead on Campaign that led to new orders or contracts from IMP, STL, SGS, Ericsson
Enhanced the TANGATE demo to highlight the advanced routing capability.
CAECO Inc. (Now part of Mentor Graphics) 1987 to 1989
• Represented CAECO in the USA and Europe.
Technical Sales Lead on Campaign that led to sales in UK, Finland and Sweden
Started a user group to help grow sales
Ferranti 1983 to 1987
• Member of a small team of engineers engaged in a variety development projects. The main focus was to develop
circuit techniques that would dramatically improve the Speed-Power product of the in house Bi-Polar
• Pioneer of differential logic from concept to production.
Development of a 3-level differential logic array
A Differential logic implementation of a Winograd FFT, a vehicle to prove comparable speed power
products to CMOS in circuits with a high degree of activity.
Logical and analog optimized design of a Bi-Polar ROM for a disk controller
Differential logic IEE presentation along with collaborating on several technical papers.
EDUCATION MSc Microelectronics systems design University of Southampton
This course was run jointly by Southampton and Brunel Universities to combine the existing
expertise in the design of digital systems and integrated circuits.
SVT and TAS sales training
VHDL, Verilog and Verilog HDL for Synthesis course
AMS Environment course
Higher National Certificate (E.Eng)
Ordinary National Certificate