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Timing and Timing Waveforms Timing Diagrams Causality and

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Timing and Timing Waveforms Timing Diagrams Causality and ...

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									 Timing and Timing Waveforms                                                   Timing Diagrams
       u   We will be discussing the following topics:                              u   A timing diagram illustrates the logical behaviour of
           – timing diagrams                                                            signals in a digital circuit as a function of time.
           – timing parameters                                                      u   Timing diagrams are an important part of the
           – derivation of timing diagrams from ASM charts                              documentation of any digital system.
           – derivation of ASM charts from timing diagrams                          u   Timing diagrams can be used both to explain the timing
                                                                                        relationships among signals within a system, and to define
           – timing waveforms and sequential logic circuits                             the timing requirements of external signals that are applied
                                                                                        to the system.




Dept of ECE, UQ                      18/04/00                             1   Dept of ECE, UQ                     18/04/00                             2




                                                                               Causality and Propagation Delay
 Causality and Propagation Delay                                               (contd.)
                                                                                    u   Previous diagram shows the delay of the two outputs with
           GO                                   READY                                   respect to the GO input.
       ENB                                      DAT                                 u   In each diagram, the upper line represents logic 1, and the
                                                                                        lower line represents logic 0.
  GO                                                                                u   Signal transitions are shown as slanted lines to remind us
                                                                                        that they do not occur in zero time in real circuits.
   READY                                                                            u   Arrows are sometimes drawn to show causality, ie, which
                          tRDY                  tRDY                                    transitions cause which outputs.
   STOP
                                                                                    u   Most important information provided is a specification of
                             tDAT                   tDAT                                delay between transitions.


Dept of ECE, UQ                      18/04/00                             3   Dept of ECE, UQ                     18/04/00                             4




 Minimum and Maximum Delays                                                    Delays (contd.)
       u   Different paths through a circuit may have different delays.             u   Delays of digital components can vary depending on the
       u   We can see that the delay from GO to READY is less than                      voltage, temperature, and manufacturing parameters. Thus,
           GO to DAT.                                                                   delay is seldom specified as a single number.
       u   As we shall see later, the delay through any given path                  u   Instead, a timing table may specify a range of values by
           may vary depending on whether the output is changing                         giving minimum, typical, and maximum values for each
           from LOW to HIGH or from HIGH to LOW (not shown in                           delay.
           this diagram).                                                           u   This carries over into the timing diagram by showing the
       u   The timing diagram is normally accompnied by a timing                        transitions to occur at uncertain times.
           table that specifies each delay amount and the conditions
           under which it applies.


Dept of ECE, UQ                      18/04/00                             5   Dept of ECE, UQ                     18/04/00                             6
 Minimum and Maximum Delays                                                      Uncertain Transitions
                                                                                      u    For some signals, the timing diagram need not show
          GO                                    READY                                      whether the signal changes from 1 to 0, or 0 to 1 at a
      ENB                                       DAT                                        particular time, only that a transition occurs at that time.
                                                                                      u    Any signal that carries a bit of “data” has this characteristic
                                                                                           - the acutal value of the data bit varies according to
      GO                                                                                   circumstances but, regardless of the value, the bit is
  READY                                                                                    transferred, stored, or processed at a particular time
                                                                                           relative to “control” signals in the system.
     DAT
                          tDATmin

                             tDATmax
Dept of ECE, UQ                      18/04/00                              7    Dept of ECE, UQ                       18/04/00                               8




 Uncertain Transitions (contd.)                                                  Bus Sequence Timing

           /WRITE                                                                  Clear


          DATAIN                                                                   Count

                                                                                               FF           00         01        02            03
      DATAOUT
                                                                                    Step

                                                                                                                 What is missing from this diagram?
Dept of ECE, UQ                      18/04/00                              9    Dept of ECE, UQ                       18/04/00                               10




 Propagation Delay                                                               Propagation Delay (contd.)
      u   The propagation delay of a signal path is the amount of                     u    The following diagram shows the two different
          time that it takes for a change in the input signal to produce                   propagation delays for the input-to-output path of a CMOS
          a change in the output signal.                                                   inverter, depending on the direction of the output change.
      u   A complex logic element with multiple inputs and outputs                          – tPLH the time between an input change and the
          may specify a different value of tP for each different signal                       corresponding output change when the output is
          path.                                                                               changing from LOW to HIGH.
      u   Different values may be specified for a particular path,                          – tPHL the time between an input change and the
          depending on the direction of the output change.                                    corresponding output change when the output is
                                                                                              changing from HIGH to LOW.



Dept of ECE, UQ                      18/04/00                              11   Dept of ECE, UQ                       18/04/00                               12
 Propagation Delays (contd.)                                                                              Causes of Propagation Delay.
                                                                                                                u   The rate at which transistors change state is influenced by:
    Vin                                                                                                              – semiconductor physics of the device
                                                                                                                     – the circuit environment, including
                                                                                                                         » input-signal transition rate
                                                                                                                         » input capacitance
                                                                                                                         » output loading
     Vout                                                                                                       u   Non-zero rise and fall times require some time to cross the
                                                                                                                    region between states.
                            tPHL
                                                                     tPLH



Dept of ECE, UQ                                        18/04/00                                     13   Dept of ECE, UQ                        18/04/00                           14




 Causes of Propagation Delay
 (contd.)                                                                                                 Timing Waveforms
      u    If the device’s operation may be adversely affected by                                               u   Let’s look at the following circuit:
           slow rise and fall times, the delays are specified at the
           logic level boundary points.                                                                             A         B         C         D        E




            HIGH

                                                                                                            l   Assuming a uniy delay in each gate, what does the
                                                                                                                timing diagram look like?
            LOW                                    tpw(min)



Dept of ECE, UQ                                        18/04/00                                     15   Dept of ECE, UQ                        18/04/00                           16




      Inverter Chains                                                                                           Inverter Chains
               1                 0             1             0           0
       A
                    B                C             D             E                                              Time      1       X         X         X         X             X
                                                                             X                                            1       0         X         X         X             X
                                                                                                                          1       0         1         X         X             X
            Odd # of stages leads to ring oscillator                                     Output high                      1       0         1         0         X             X
            Snapshot taken just before last inverter changes                            propagating                       1       0         1         0         1             X
                                                                                       thru this stage
                                                                                                                                                                              0
                                                                                                                          0       0         1         0         1
   Timing Waveform:
                                                                                                                          0       1         1         0         1             0
                                             Period of Repeating Waveform ( tp)                                           0       1         0         0         1             0
                                                                    Gate Delay ( td)
                                                                                                                          0       1         0         1         1             0
                        A (=X)   0       1                                                                                0       1         0         1         0             0
                                                                                                                                                                              1
                        B        1

                        C        0                                                                                        Propagation of Signals through the Inverter Chain
  tp = n * td
  n = # inverters       D        1

                        E        0


Dept of ECE, UQ                                        18/04/00                                     17   Dept of ECE, UQ                        18/04/00                           18
 ASM Charts and Timing
 Diagrams                                                                 Problem #1 (again!)
      u   Let us use the same diagram with which we completed the
          last lecture.                                                                      A        CMD1
      u   Using this ASM chart, what does the timing diagram look
          like, and how do we derive it?
      u   Also, what are the problems we need to be alert to when                                                1
                                                                                                             Z
          we implement the system?
                                                                                                         0
                                                                                                       CMD2


                                                                                             C         CMD3             B

Dept of ECE, UQ                   18/04/00                          19   Dept of ECE, UQ                     18/04/00                            20




 Timing Diagram                                                           Points to Note
                                                                               u   The input Z must be synchronous, otherwise the value may
          clock                                                                    not be read correctly.
          state   c     a     b      a    c      a                             u   What are the effects of this? We will begin to discuss this
                                                                                   soon in the next lecture.
          Z

          CMD1

          CMD2

          CMD3




Dept of ECE, UQ                   18/04/00                          21   Dept of ECE, UQ                     18/04/00                            22




 What did we cover?
      u   You tell me!




Dept of ECE, UQ                   18/04/00                          23

								
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