Tutorial 4 Solution

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```					                                       Tutorial 4 Solution
Subject: Telecommunication Networks I - ECTE 364;
Computer Networking - ECTE 483

1-   Prove that the minimum distance of a parity-check code is 2. How many bit errors this code can detect? How many
it can correct?

Consider two (valid) codewords associated with a parity-check code (a codeword is
comprised of the data bits plus a single parity bit added). In the case of even or odd
parity, the total number of 1’s in these codewords is even or odd respectively.

We will now demonstrate that the distance between these two codewords cannot be
one. Assume to the contrary that the distance between these two codewords is one.
This means that all but one of the bits between these two codewords are the same.
The one bit that is different is 0 in one and 1 in the other codeword. However, this
means that both codewords cannot have valid parity. Hence, the distance between
the codewords is greater than one.

We will now demonstrate that two valid codewords can have a distance of two.
Consider the case as before when all the bits are the same except for two bits. These
two bits can be 00, 01, 10, 11 in one codeword and 11, 10, 01, 00 respectively in the
other. In all cases the parity of the codeword is preserved.

Given that the minimum distance between two parity-check codewords is greater
than 1 then we have shown that it is two. With a min distance of two, we can detect
one bit error (in the case of parity, we can actually detect any odd number of bit
errors). It is not possible to correct errors with this min distance.
2-   Consider an error-free 64-kbps satellite channel used to send 512-byte data frames in one direction with very short
acknowledgements coming back the other way. What is the maximum throughput for window sizes of 1, 7, 15 and 127?

A 512 byte (4096 bits) data frame has a duration of 4096/64000 seconds – that is 64 msec.
Assume that the satellite is at 36000 km distance. This leads to roundtrip propagation time
of 240 msec. We should also add 64 msec to this to account for transmission time.
Hence with a window size of 1, 4096 bits can be sent every 240+64=304 msec. This
equates to the throughput of 4096 bits/304 msec or 13.5 kbps.
For a window size greater than 5, the full 64 kbps is used.

3-   Two adjacent nodes (A and B) use a sliding window protocol and a 3-bit sequence number. As the ARQ
mechanism, go-back-N is used and the window size is 4. Assume A transmits and B receives, show the window
positions for the following succession of events:
a)   Before A sends any frames.
Note that it is entirely possible to have a window size different to that provided by the
sequence number. In this case, even though a window size of 8 frames is possible (3-bit
sequence number), the window size is restricted to 4.
Transmission window prior to any frames being transmitted is:
…             0 1 2 3 4 5 6 7 0 1 2 3 4                                                             …

b)   After A sends frames 0, 1, 2 and B acknowledges 0, 1 and the ACKs are received by A.
If B acknowledges frames 0 and 1, it would do so using an RR2. This tells the transmitter
that the receiver can accept 4 frames (window size) starting from frame 2. Node A has
already sent frame 2 and although it has not been acknowledged, there is nothing to
indicate that frame has been lost or corrupt. Node A should assume frame 2 is still in
transit. Accordingly, the transmitter can grow its window by 2 frames.

…             0 1 2 3 4 5 6 7 0 1 2 3 4                                                             …

c)   After A sends frames 3, 4, 5 and B acknowledges 4 and the ACK is received by A

Acknowledgement of frame 4 would be done using an RR5. This means the receiver is
ready for four frames starting from frame 5. Since frame 5 has already been transmitted,
the transmitter window looks like this:

…             0 1 2 3 4 5 6 7 0 1 2 3 4                                                             …

4-   What is the purpose of using modulo 2 arithmetic rather than binary arithmetic for computing an FCS?

Any arithmetic process would work provided it is applied the same way in the forward
and reverse process. Modulo 2 is easy to implement in hardware.
5-   Data link protocols almost always place the CRC in a trailer, rather than in the header. Why?

The CRC is computed during transmission and it is easier to be appended to the end of
the frame as soon as the last bit goes out onto the wire. If it were in the header, the entire
Thus, each frame would have to be handled twice.
6-   Using the CRC-CCITT polynomial, generate the 16-bit CRC code for a message consisting of a 1 followed by 15
0s’;
a)   using long division, and

The CRC-CCITT polynomial is:                  P( x) = x16 + x12 + x 5 + 1 . We have,
M(x) = 1000 0000 0000 0000 and                 x n M ( x) = x 31
Long division:

Code is 0001101110011000.

b)   using the shift register mechanism.

The shift register would look like:
7-   Consider the use of 1000-bit frames on a 1Mbps satellite channel with a 270 millisecond delay. What is the
a) Stop-and-wait flow control?
b) Sliding window flow control with a window size of 127?

1000 bits/frame, rate = 1 Mbps, propagation delay 270 msec.

Propagation delay 270 ×10 −3
First we calculate     a=                  =           = 270
Transmission time 1000 / 106
1
Then for stop and wait: U   =          = 0.002 or 2%.
1 + 2a
W
And for sliding window: U   =          = 0.23 or 23%.
1 + 2a

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Description: Tutorial 4 Solution