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									  Digitally Controlled Power Supplies
Introduction and design considerations

                David Figoli
             Shamim Choudhury

            Digital Power Systems
             Texas Instruments
                    Houston


                                    TEXAS INSTRUMENTS
Agenda
    Technology Overview
    Hardware
    Software
    Control Theory



                           TEXAS INSTRUMENTS
                 Scope of Digital Power Control
              Telecom infrastructure                              “Equipment”

               Base stations
                                                                  Mother boards
      
              Servers                                               DC/DC
              Routers                                                POL

              Workstations
               Industrial
                                   400KHz ~ 1MHz
                                                                    DC/DC
                                                                      POL

               100KHz ~ 200KHz      200KHz ~ 500KHz



85 ~ 265   F                      DC / DC            IBC
  VAC      I                                               6~14
           L                                48 VDC         VDC
           T
                            PFC                                      DC/DC
           E                                                          POL
           R



                                                                  TEXAS INSTRUMENTS
           Full Digital control system
    0110101100                   • Resolution
    1011011101                   • Topology support
    0010100111                   • “speed”



                                       DAC
    Digital
   Controller
                                       ADC
                                                               “Plant”

• MIPS “engine”                      • Resolution
• “C” (HLL) Efficiency               • Linearity / Accuracy
• Data size (e.g. 16/32 bits?)       • Speed (sampling rate)
                                                                  TEXAS INSTRUMENTS
                       Time sampled systems
                               Digital Controller

                               -              Control
       A-D                                    Law
                                                                 D-A
                               +
                                   Ref


y(t)                    y(n)                       y(n)          y(t)
                                         sample
                                          period
                                            T




                x(t)                        x(n)          x(n)                     x(t)
  Continuous                Discrete
  time signal             time signal




                                                                        TEXAS INSTRUMENTS
     Time Division Multiplexing – TDM         (1/2)


    y(n)

              TSAMPLE




                                             x(n)


Processor   Control Code   Control Code      Control




                                          TEXAS INSTRUMENTS
     Time Division Multiplexing – TDM                           (2/2)

     y(n)
                   TSAMPLE




                                                                  x(n)


Processor 1   Control Code (C1)        Control Code     Control

Processor 2   Control Code (C2)        Control Code     Control


Processor 3   Control Code (C3)        Control Code     Control


Single CPU    C1     C2      C3   C1       C2     C3   C1      C2        C3




                                                            TEXAS INSTRUMENTS
                 F280x - Digital Controller engine
Code security                    F280x                                6 timers  6 phases
 64Kw Flash +       10Kw        4Kw                       EPWM x 6    12 PWMs  12 x Vout
 Emulated EE        RAM         Boot
                                ROM                                   4 of 12  HiRes PWM
                                                          APWM x 4
XINTF
              Memory Bus
                                                          ADC (12b)   4 timers  4 phases
                                         Peripheral Bus               4 PWMs  4 x Vout
                                                            GPIO
         Interrupt Management


   100 MIPs C28xTM 32-bit DSP                                         12 bit @ 12.5 MSPs
    32x32-bit         RMW                                SCI x 2
    Multiplier        Atomic
                       ALU                                 CAN x 2
      32-bit
                                                           SPI x 4
                                                                      PMBus
    Timers (3)
                       32-bit
        Real-Time     Register                               I2C
          JTAG          File




                                                                                  TEXAS INSTRUMENTS
                   PWM resources – F2808
Ext (optional)


   SyncI         HR-PWM-1A
EPWM1                                                        10 timebases
                                                              10 independent freq.
   SyncO         EPWM-1B



   SyncI         HR-PWM-2A         SyncI
                                                              10 phase Interleaved
EPWM2                           APWM1            APWM1         ( 36o phase offset )
   SyncO         EPWM-2B          SyncO




   SyncI         HR-PWM-3A         SyncI
                                                             16 independent duty
EPWM3                           APWM2            APWM2        16 Vout rails
   SyncO         EPWM-3B          SyncO                       10 independent freq.
                                                              4 with HiRes PWM
   SyncI         HR-PWM-4A         SyncI

EPWM4                           APWM3            APWM3
   SyncO         EPWM-4B          SyncO
                                                             Combinations
   SyncI         EPWM-5A           SyncI
                                                              1x6phase / 4xSingle
EPWM5                           APWM2            APWM4        2x3phase / 4xSingle
   SyncO         EPWM-5B          SyncO                       3x3phase / 1xSingle
                                   Future
                                                              3x3phase / 7xSingle*
   SyncI         EPWM-6A         expansion

EPWM6
   SyncO         EPWM-6B


Ext (optional)               Note: F2809 will have 6 HRPWM

                                                                        TEXAS INSTRUMENTS
      Example: AC/DC – Rectifier Control
              VAC   VRECT                                  IPRI    VBOOST
                                                                                                       VOUT
                                                                   CT




      F
      I                                                           EPWM1A      EPWM2A
      L
                            APWM1    APWM2
      T
      E
      R
                                                                  EPWM1B       EPWM2B


                                    Diode          Diode                                A
            IPFC                    clamp          clamp                    VOUT(P)
                                            IphA            IphB

                                                   Primary Side Controller
•   1000W                                             A                 P
•   F280x DSP based                                   D
                                                      C  F280x
                                                                        W
                                                                        M
                                                         Digital
•   2 phase interleaved PFC                           I Controller
                                                                        C
                                                                        O
                                                                                                I2C
                                                                                                CAN
•   Phase shifted ZVS-FB
                                                                        M
                                                      O                 M                       SCI
                                                                        S                       SPI
•   200 KHz PWM (DC/DC)
•   100 KHz PWM (PFC)

                                                                                            TEXAS INSTRUMENTS
                    Example: DC/DC Control
             Duty Cycle
2 pole                                            4
                                              3                            Vout4
2 zero   D1                       1       2                          Vout3
CNTL                      EPWM1
                                  1               Vin              Vout2
                                                                 Vout1
2 pole
2 zero   D2                       2   1               GATE

CNTL                      EPWM2                       DRV

                                  2
2 pole
2 zero   D3                       3               4
                          EPWM3               3                              Vout
CNTL                              3       2
                                                  Vin
2 pole
2 zero   D4                       4
CNTL                      EPWM4
                                  4   1               GATE
                                                      DRV


2 pole
2 zero   D
CNTL
                          APWM1   1           3
                                          2                                Vout
                                                  Vin
2 pole
2 zero   D                APWM2   2
CNTL                                  1               GATE
                                                      DRV




                          APWM3   3



                                                             TEXAS INSTRUMENTS
      A closer look ....
    0110101100               • Resolution
    1011011101               • Topology support
    0010100111



                                   DAC
    Digital
   Controller
                                   ADC
                                                        “Plant”

• MIPS “engine”               • Resolution
• “C” Efficiency              • Linearity / Accuracy
• Data size (e.g. 32 bits)    • Speed (sampling rate)
                                                           TEXAS INSTRUMENTS
  Digital
 Controller
                               Processor consideration
                    TPWM



PWM                                                             # Inst. vs Algorithm
                                                                  S/W algorithm       clks
CPU           Control Code spare Control Code spare   Control   Controller             25
                                                                (2 pole / 2 zero)
                                                                Controller (3P/3Z)     29
# Instructions vs PWM
                                                                PFC Current loop       48
     PWM freq.          PWM per.        Processor MIPS
       (KHz)              (uS)        40      100     150       IIR filter             23
         50               20.0        800    2000    3000       PSFB (ZVS) PWM         14
         100              10.0        400    1000    1500       driver
         200               5.0        200     500     750       Multi-phase (N) IL    7+2N
         250               4.0        160     400     600       PWM driver.
         300               3.3        133     333     500
         500               2.0        80      200     300       PFC2PHIL PWM           26
         750               1.3        53      133     200       driver
        1000               1.0        40      100     150
 MIPS = Million Instruction Per Second

                                                                              TEXAS INSTRUMENTS
           CPU Performance requirements                                                                              (1/2)

  ISR Bandwidth utilization = TISR / TSAMPLE * 100%
y(n)
                    TSAMPLE

                                                      TISR



                                                                                                x(n)
        Interrupt


 CPU                 ISR            BG                 ISR                 BG        ISR




               CS ADC Ack           Loop1         Loop2          Loop3                   PWM    CR


                                  controller-1                  controller-3
                                                                                               Context Restore +
   Context Save +
                        ADC service +                                           DPWM              Int Return
     Int latency
                          Int Ack                controller-2                   access

            Operation                   # Clock Cycles             # Clock Cycles          # Clock Cycles
                                            (1 loop)                  (2 loops)               (3 loops)
    Context Save + Int. latency                16                         16                      16
       ADC servicing + Ack                      4                          5                       6
         2P/2Z controller                      25                         47                      69
         DPWM access                            4                          8                      12
   Context Restore + Int. Return               16                         16                      16

               Total                             65                        92                      119
                                                                                                                   TEXAS INSTRUMENTS
CPU Performance requirements                                               (2/2)



ISR Utilization for PWM frequency vs # Control loops
CPU clk = 100 MHz            10 nS

      PWM                             # LOOPS & # Cycles
  (KHz)     (uS)        1              2       3          4           5
                        65             92     119        146         173
  200       5.00       13%            18%     24%        29%         35%
  300       3.33       20%            28%     36%        44%         52%
  400       2.50       26%            37%     48%        58%         69%
  500       2.00       33%            46%     60%        73%         87%
  600       1.67       39%            55%     71%        88%        104%
  700       1.43       46%            64%     83%       102%        121%
  800       1.25       52%            74%     95%       117%        138%
  900       1.11       59%            83%    107%       131%        156%
  1000      1.00       65%            92%    119%       146%        173%
  1100      0.91       72%           101%    131%       161%        190%

Note: Entries in red require more than 100% and are not possible.




                                                                     TEXAS INSTRUMENTS
ADC                ADC consideration

ADC utilization - # Channels (“Loops”) vs PWM freq.
      MSPS = 3                MSPS = 6.25                      MSPS = 12.5
   PWM        # Channels   PWM         # Channels           PWM        # Channels
   (KHz)                   (KHz)                            (KHz)
    125           24         125           50                 125          100
    250           12         250           25                 250           50
    500            6         500           13                 500           25
    750            4         750            8                 750          16.7
    1000           3        1000            6                1000          12.5


                                                    ( Note: 12.5 MSPS = 80 nS conversion )




                                                                     TEXAS INSTRUMENTS
Example: ADC capability of F280x
   ChA1
   ChA2                                                      Result
   ChA3    M
           U
                  S/H                                       registers
           X      “A”                                        Result 0
                                                             Result 1
   ChA7                                                      Result 2
                            ADC        Sequencer
   ChB1
   ChB2
   ChB3    M
           U
                  S/H                                        Result 7
           X      “B”                                        Result 8

   ChB7
                                                             Result 14
                                                             Result 15

   F280x – on chip ADC
   • 12 bit resolution / Pipeline architecture / Dual S/H
   • up to 12.5 MSPS / 80 nS conversion
                            A D C


   • 16 Analog channels
   • Programmable S/H apperture window
   • Start of Conversion (SOC) trigger via PWM timer
   • SNR = 67dB / THD = -74dB
   • DNL = +/- 1LSB, INL = +/- 1.5LSB, Offset = +/- 4LSB

                                                                TEXAS INSTRUMENTS
DAC                    PWM consideration
                                                   V
                   TPWM
                                                                      VSTEP

PWM      TSysclk
                                          t                               t
       PWM resolution = Log2 ( TPWM / TSysClk )

                                                 280x PWM
      PWM Freq       Regular resolution        High resolution
        (KHz)         (bits)     (%)          (bits)       (%)
         200           9.0       0.2          15.0        0.003
         250           8.6       0.3          14.7        0.004
         300           8.4       0.3          14.4        0.005
         500           7.6       0.5          13.7        0.008
         750           7.1       0.8          13.1        0.011
        1000           6.6       1.0          12.7        0.015
        1500           6.1       1.5          12.1        0.023
        2000           5.6       2.0          11.7        0.030
                                                                  TEXAS INSTRUMENTS
    Example: Regular vs High Res PWM

                                        280x System Clock = 100 MHz
     Hi-Resolution
                                        PWM freq = 10 MHz
        PWM                             Period = 10 clocks
                                        (i.e. 10 step resolution)

                                        Voltage resolution = 3.3V/10
                                                           = ~300mV
                           300 mV



                Conventional
                   PWM




Voltage output shown as ramp function



                                                       TEXAS INSTRUMENTS
Limit Cycle Oscillation in Digital Power Converter
                    Vo levels (DPWM duty
                                         ADC levels          error bins
                          ratio steps)
       Volt
              ΔVc                                  ΔVs        +0010
                                                   ΔVs        +0001
       Vref                                                    0000
              ΔVc
                                                              -0001
                                      steady state output,
                                      limit cycle              time


                  Vo levels (DPWM duty ADC levels
                        ratio steps)                         error bins
       Volt    ΔVc
                                              ΔVs              +0010
                                              ΔVs              +0001
       Vref                                                     0000
                                                               -0001
                                       steady state output,
                                       no limit cycle       time


                                                                          TEXAS INSTRUMENTS
      Example: Closed loop HiRes PWM
                                                                       Single Power Stage
Watch Window            Voltage                  HR
                                                          E
                       Controller                         P            Vin1                             Vout1
                                                BUCK      W
                            CNTL                 DRV      M
                            2P2Z
               Vref                                       H
    Vref              Ref      Uout   DutyCmd   Duty      W   EPWMnA       DRV                 Buck
                      FB
   DutyCmd                                      1 MHz
                      1 MHz
                                                  ADC     A
                                                          D
                                                  1CH
                                                          C
                                                  DRV
                                                          H
                                       Vout     rslt0     W     Ch0

                                                1 MHz



  HiRes (150pS) PWM                                     Regular (10nS) PWM




                                                                                            TEXAS INSTRUMENTS
   Example: HiRes PWM – a closer look




Non-HiRes           HiRes




                                TEXAS INSTRUMENTS
  Resolution loss - low duty utilization
                             TPWM
          Max Duty


PWM                                     Not Utilized

                                                                          t
        TSYSCL (10 nS)

                                    Vout
          0.8            1   1.2      1.8       2.5    3.3          5
  Vin   Resolution Loss in bits
  14      4.1        3.8     3.5      3.0       2.5    2.1          1.5
  12      3.9        3.6     3.3      2.7       2.3    1.9          1.3
  10      3.6        3.3     3.1      2.5       2.0    1.6          1.0
  9       3.5        3.2     2.9      2.3       1.8    1.4          0.8
  8       3.3        3.0     2.7      2.2       1.7    1.3          0.7
  7       3.1        2.8     2.5      2.0       1.5    1.1          0.5
  6       2.9        2.6     2.3      1.7       1.3    0.9          0.3


                                                             TEXAS INSTRUMENTS
Hardware ...


          TEXAS INSTRUMENTS
                       AC/DC - Rectifier
              VAC   VRECT                                  IPRI    VBOOST
                                                                                                       VOUT
                                                                   CT




      F
      I                                                           EPWM1A      EPWM2A
      L
                            APWM1    APWM2
      T
      E
      R
                                                                  EPWM1B       EPWM2B


                                    Diode          Diode                                A
            IPFC                    clamp          clamp                    VOUT(P)
                                            IphA            IphB

                                                   Primary Side Controller
•   1000W                                             A                 P
•   F280x DSP based                                   D
                                                      C  F280x
                                                                        W
                                                                        M
                                                         Digital
•   2 phase interleaved PFC                           I Controller
                                                                        C
                                                                        O
                                                                                                I2C
                                                                                                CAN
•   Phase shifted ZVS-FB
                                                                        M
                                                      O                 M                       SCI
                                                                        S                       SPI
•   200 KHz PWM (DC/DC)
•   100 KHz PWM (PFC)

                                                                                            TEXAS INSTRUMENTS
        Common & Diff. mode filter


                                                                PFC_IN
1




         1   4
    3
         2   3
2




                                                       4      PFC_R ET
                                              1
                                                       3
                                              5
                          +1 2V




                                  1
                                              2



                 AC -N




                                       2
                                  2
                                                  1         RELAY-CNTL

                                                              ( G PIO )




                                       3
                                       PR I

                                      In-Rush Relay




                                                      TEXAS INSTRUMENTS
                                           Interleaved Boost Converter
                                                                                                                           2             1                             V- BO OST




                                           1



                                                    1
                                                                                                                           2             1               +         +



                                                                                                                                   +3 V3 +3 V3


                                           2



                                                    2
                       PFC_ IN

                       PFC_ RET            1                                  IPFC                                                                    PR I      PR I



                                                    1                                                                  2       1                                  I-PH A-SENSE
                                                                               PFC_ ISENSE                                                                       ( A DC-I NA? )
                                                                              PFC_ ISENSE_ GND




                                                                                                                2
                                                                                                                                                  +3 V3 +3 V3
                                           2



                                                    2




                                                                                                            1
                                                                                                                                         PR I




                                                                                                                3
               PWM                                                              PR I
                                                                                                                       2       1                                  I-PH B-SENSE
                                                                                                                                                                  ( A DC-I NA? )




                                                                                                     2
                PFC               U7
                                                               +1 2V

                             2                            13                                     1
                                  3V3- ou t       VD D    12
                                                 PVDD                               PR I




                                                                                                     3
PFC-A ( A PWM1 )             3                            11                                                                                            PR I
                                  IN1            OUT1
PFC-B ( A PWM2 )             5                            10
                                  IN2            OUT2                                                PR I       PR I
I-LIM-FLAG ( G PIO )         6
                                  CL F                                                                                                           IPHA & B
I-PF C-SET                   7                            8           PFC_ ISENSE
                                  I-L IM       I-SEN SE
( E PWM3 A )                 1                            9
                            14    N/C            PG ND    4
                                  N/C            AG ND

                                  UCD 72 01
               PR I                                            PR I




                                                                                                                                                  TEXAS INSTRUMENTS
                                 Phase Shifted Full Bridge                +3 V3




                     IDCDC                         1           2                        I-DCDC-SENSE
                                                                                        ( A DC-I NA? )




                                               5



                                                       8
                                                                          PR I
VBOOST




                                               1



                                                       4
                                                                                                                                                                        VO UT
                        FB ga te dr iv e1 _2




                                                                                  2




                                                                                                            2




                                                                                                                                        1




                                                                                                                                                1
FB-LHS   ( E PWM1 A )
                            IN- HS                     L- HS              1                             1
FB-LLS   ( E PWM1 B )                 OUT- HS
                            IN- LS                     L- LS




                                                                                  3




                                                                                                            3
                                      OUT- LS
                            EN                                                                                          8   4




                                                                                                                                        2




                                                                                                                                                2
                                                                                                                        5   1




                                                                                  2




                                                                                                            2




                                                                                                                                        1




                                                                                                                                                1
                                                                          1                             1
                        FB ga te dr iv e2 _2




                                                                                  3




                                                                                                            3




                                                                                                                                        2




                                                                                                                                                2
FB-RHS (EP WM2A )
                            IN- HS                     R- HS
FB-RLS   (EP WM2B )                   OUT- HS                                    PR I                       PR I                                      SEC
                            IN- LS                     R- LS
FB-EN    ( G PIO )                    OUT- LS                                                               HCN R20 0
                            EN




                                                                                                                1
                                                                                                                                                            HCN R20 0

         PWM                                                                            PR I

         PSFB




                                                                                                                                                                    2
                                                                                                    3




                                                                                                                2
                                                               V-OUT-SENSE                      +

                                                               ( A DC-I NA? )                       2                                                        1
                                                                                                -




                                                                                                                                                                    3
                                                                                                                                            2   -




                                                                                                                                  2
                                                                                                                                            3   +




                                                                      VOUT
                                                                                                                                  1
                                                                                                                                HCN R20 0

                                                                                                                                                SEC


                                                                                                                                                      TEXAS INSTRUMENTS
                    Signal Conditioning / DSP Interface
PFC_IN                                                   V-AC-SENSE                                                                                                                F280x
                                                                                                                                                                         UCD 9501 / 2801 - Partial view

                                                                                                                                                          V-AC-SENSE                                        FB-LHS
                                2   -                                I-D CDC                                                         +3V3                                   AD CIN-A0           EPWM1A
                                                                                                                                                          V-PFC-SENSE                                       FB-LLS
                                3   +                                                                                                                                       AD CIN-A1           EPWM1B
                                                                                                                                                          I-PF C-SENSE
                                                                                  +2V5_Ref                                                                                  AD CIN-A2                       FB-RHS
AC -N                                                                                                        3                                            I-PHA-SENSE                           EPWM2A
                                                                                                                 +                                                          AD CIN-A3                       FB-RLS
                                                                                                             2                                            I-PHB-SENSE                           EPWM2B
                                                                                                                 -      Comparator                                          AD CIN-A4
                                                                                                                                                          I-DCDC-SENSE                                     I-PF C-SET
+5V                                                         I-D CDC-SET                                                                                                     AD CIN-A5           EPWM3A

                                                            ( E PWM3 B )                                                                                  V-OUT-SENSE                                     I-DCDC-SET
                                                                                                                                                                            AD CIN-A6           EPWM3B
                                     +2V5_Ref
                2   -                                                                                                                                                       AD CIN-A7                       PFC-A
                                                                                                                                                                                                APWM1
                3   +                                                                                                                                                       AD CIN-B0                       PFC-B
                                                                                      PR I   PR I                                                                                               APWM2
                                                                                                                                                                            AD CIN-B1
                                                                                                                                                                                                          RELAY-CNTL
                                                                                                                                                                            AD CIN-B2             GPIO
                                                                                                                                                                                                           I-LIM-FLG
                                                                                                                                                                            AD CIN-B3             GPIO
PR I     PR I                                                                                                                                     +3V3
                                                           V-BOOST                                                                                                          AD CIN-B4

                                                                                                                                                                            AD CIN-B5
                                                                                                        V-PFC-SENSE
                                                                                                                                                                            AD CIN-B6
I-PFC                                     I-PF C-SENSE
                                                                                                                                                                            AD CIN-B7

                                                                                  2   -                                                                    I-DCDC-TRIP
                        2   -                                                                                                        3                                      TZ1 (tr ip z one)
                                                                                  3   +                                                  +                 V-PFC-TRIP
I-PFC-GN D              3   +                                                                                                        2                                      TZ2
                                                                                                    +2V5_Ref                             -   Comparator
                                                                                                                                                                            TZ3

                                                                                                                                                                            TZ4

                                                                PR I       PR I                                                                                          <Value>
                                                                                                                     V-PFC-SET
                                                                                                                                                                           (partial view)
                                          PR I




                                                                                                      PR I       PR I



                                                                                                                                                                              TEXAS INSTRUMENTS
                                        F280x “Life support”
                                                                                                                    10 x 0.1uF ceramic
          AD CIN- A0                                  AD 0                       3V3
          AD CIN- A1
          AD CIN- A2
          AD CIN- A3                                                                                                                                                                    3V3
          AD CIN- A4
          AD CIN- A5                                                U1 2
          AD CIN- A6                                          23                                         96
          AD CIN- A7                                          22    AD CIN- A0     Flash VD D3VFL
3V3                                                           21    AD CIN- A1                           3                                                                      50 uH
                                                              20    AD CIN- A2         3V3    VD DIO1    46                                                                     50 uH
      5                    4                                  19    AD CIN- A3         I/O    VD DIO2    65                                                                     50 uH   1V8
           VC C   CL MP1   6                                  18    AD CIN- A4                VD DIO3    82                                                                     50 uH
                  CL MP2   3                                  17    AD CIN- A5                VD DIO4
      2           CL MP3   1                                  16    AD CIN- A6                           10                                                                     50 uH
           GND    CL MP4                                      27    AD CIN- A7                  VD D2    42                                                                     50 uH
                                                              28    AD CIN- B0     1V8          VD D3    59                                                                     50 uH
      5                    4                                  29    AD CIN- B1     Core         VD D4    68                                                                     50 uH
           VC C   CL MP1   6                                  30    AD CIN- B2                  VD D5    85                                                                     50 uH
                  CL MP2   3                                  31    AD CIN- B3                  VD D6    93                                                                     50 uH
      2           CL MP3   1   AD 0                           32    AD CIN- B4                  VD D7
           GND    CL MP4                                      33    AD CIN- B5                           78               RESET
          NUP42 0MR 6                 2u 2                    34    AD CIN- B6                  XR Sn
                                                                    AD CIN- B7                           88
                                      2u 2                    37                                   X1    86
                                                              36    AD C- REFP                     X2
                                      22 K1 , 1 %             38    AD C- REFM                           90                        1M
                                                              24    AD C- RESEXT               XC LKIN   66
                                                              35    AD C- LO                 XC LKOUT
                                              10 0n                 AD C- REFIN                          97
            EPWM1 A                                           47                                TEST1    98                               30 MHz
            EPWM1 B                                           44    GPIO -0 0                   TEST2                             33 p                   33 p
            EPWM2 A                                           45    GPIO -0 1                            84
            EPWM2 B                                           48    GPIO -0 2                  TR STn    75
            EPWM3 A                                           51    GPIO -0 3                    TC K    74
            EPWM3 B                                           53    GPIO -0 4                    TMS     73
            EPWM4 A                                           56    GPIO -0 5                     TD I   76
            EPWM4 B                                           58    GPIO -0 6                    TD O    80                                        3V3          1V8A
            EPWM5 A                                           60    GPIO -0 7                   EMU0     81
            EPWM5 B                                           61    GPIO -0 8                   EMU1
            EPWM6 A                                           64    GPIO -0 9
            EPWM6 B                                           70    GPIO -1 0                            26                       50 uH
            TZ1                                                1    GPIO -1 1                VD DAIO     25
            TZ2                                               95    GPIO -1 2                VSSAIO      12                       50 uH
            TZ3                                                8    GPIO -1 3               VD D1A18     40                       50 uH
            TZ4                                                9    GPIO -1 4               VD D2A18     13
                                                                    GPIO -1 5             VSS1 AGN D     39
            SPI-SIMO                                                                      VSS2 AGN D
                                                              50                                         15                                          +            +
            SPI-SOMI                                          52    GPIO -1 6                 VD DA2     14
            SPI-C LK                                          54    GPIO -1 7                 VSSA2                                                      4u 7         4u 7
            GPIO -1 9                                         57    GPIO -1 8
            GPIO -2 0                                         63    GPIO -1 9                            2
            GPIO -2 1                                         67    GPIO -2 0                   VSS2     11                                                                                       1V8              1V8A
            GPIO -2 2                                         71    GPIO -2 1                   VSS3     41
            GPIO -2 3                                         72    GPIO -2 2                   VSS4     49
            APWM1                                             83    GPIO -2 3                   VSS5     55                                               U8                              2.2 u            50 uH
            APWM2                                             91    GPIO -2 4                   VSS6     62   Vin (5 V)                             1                           3                                           3V3
            APWM3                                             99    GPIO -2 5                   VSS7     69                                               Vin         Vo ut1    4
            APWM4                                             79    GPIO -2 6                   VSS8     77                                         8                 Vo ut2
            SC I- RX                                          92    GPIO -2 7                   VSS9     87                                        10     En 2                  2
            SC I- TX                                           4    GPIO -2 8                  VSS1 0    89                                         6     En 1        Re se t
            CAN- RX                                            6    GPIO -2 9                  VSS1 1    94               0.1 u                           NR                    7                                   2.2 u
            CAN- TX                                            7    GPIO -3 0                  VSS1 2                                               5                   FB2     9
                                                                    GPIO -3 1                                                       0.0 1u                GND            NC
            SD A                                             10 0                                                                                                                                 0.0 1u
                                                                    GPIO -3 2                                                                             TPS7 13 19
            SC L                                               5
            GPIO -3 4                                         43    GPIO -3 3
                                                                    GPIO -3 4                                                                                                                                       RESET
                                                                    TMS3 20F28 08 PZ

                                                                                                                                                                                              TEXAS INSTRUMENTS
                BH2808 Contoller board

F2808 DSP controller board
   • “battle hardened” design for harsh electrical environments
   • DIMM 100 pin format
   • Isolated SCI Interface
   • JTAG port for real-time debug
   • Dimensions – 1.4” x 3.5” (35 x 89 mm)




                                                                  TEXAS INSTRUMENTS
                  Actual System hardware
                                                                         PFC
                                                   PFC
                       Bridge      Inductor 1                           Phase 2        Inductor 2
                                                  Phase 1
                        Rect.
                                                 FET+Diode
                        Con.
                 In-rush
                  relay
                                                                                                DC bus
                                           Full Bridge                   Full Bridge
                                            Left-leg                      Right-leg              Caps
                                                                                                (900uF)
                                                              Res.
                                                              Ind.
       Common / Diff mode
           chokes



                                            Output          Isolation     Output
                                            diodes        transformer     diodes



                                                         Output Ind.




  DSP                                                        Output
controller                       Voltage                      Caps
                                Feedback
                                  opto



                                                                                                TEXAS INSTRUMENTS
               Multi-phase / Output DC/DC
             Duty Cycle
2 pole                                            4
                                              3                            Vout4
2 zero   D1                       1       2                          Vout3
CNTL                      EPWM1
                                  1               Vin              Vout2
                                                                 Vout1
2 pole
2 zero   D2                       2   1               GATE

CNTL                      EPWM2                       DRV

                                  2
2 pole
2 zero   D3                       3               4
                          EPWM3               3                              Vout
CNTL                              3       2
                                                  Vin
2 pole
2 zero   D4                       4
CNTL                      EPWM4
                                  4   1               GATE
                                                      DRV


2 pole
2 zero   D
CNTL
                          APWM1   1           3
                                          2                                Vout
                                                  Vin
2 pole
2 zero   D                APWM2   2
CNTL                                  1               GATE
                                                      DRV




                          APWM3   3



                                                             TEXAS INSTRUMENTS
               DC/DC ...more details
F2808                           ILim_set-1
                                ILim_set-2
 SPI-DO                10 bit                                Vin1      Vin2
                       DAC                                   (5~12v)   (5~12v)
  SPI-DI                                                                         Top Bot.
 SPI-CLK
                       8-Ch     ILim_set-6                                       Bias Bias

                                    Top FET
 EPWM1A     PWM1                    Bias Gen.     PWM1
 EPWM2A     PWM2                                  VOUT-1
                                    Bot. FET      IPHS-1       8A Sync Buck Stage
                                    Bias Gen.    VTEMP-1                                     VOUT1
 EPWM6A     PWM6                                  Fault-1                   1
                                                 Enable-1
 ADCIN-A0   VOUT-1                              ILim_set-1
 ADCIN-A1   VOUT-2
                                                  PWM2
                                                  VOUT-2
 ADCIN-A5   VOUT-6                                IPHS-2       8A Sync Buck Stage
 ADCIN-B0   IPHS-1                               VTEMP-2                                     VOUT2
 ADCIN-B1   IPHS-2                                Fault-2                   2
                                                 Enable-2
                                   VTEMP-1
                                   VTEMP-2      ILim_set-2
 ADCIN-B5   IPHS-6
                       Analog
 ADCIN-B6
                        MUX        VTEMP-6

  GPIO      Enable-1                Vin1
  GPIO      Enable-2                Vin2

                                                  PWM3
  GPIO      Enable-6                              VOUT-6
  GPIO      Fault-1                               IPHS-6       8A Sync Buck Stage
  GPIO      Fault-2                              VTEMP-6                                     VOUT6
                                                  Fault-6                   6
                                                 Enable-6
  GPIO      Fault-6                             ILim_set-6


                                                                                    TEXAS INSTRUMENTS
                    The Power stage
            8A Synchronous Buck power stage
   Vin
 (5~12v)

                        Circuit
  Fault                Breaker
Top Bias                Logic
Bot. Bias




  PWM
               UCD7230
 Enable                                                  VOUT
             Digital Control
              Gate Driver
                                                       8A
ILim_set
                                                       max

                                                         Ret
  IPHS
                                  Temp
 VTEMP                            sensor

  Vout                                     Diff Amp




                                                      TEXAS INSTRUMENTS
UCD7230 gate driver




                      TEXAS INSTRUMENTS
6 ch power EVM + 2808 ezDSP




                         TEXAS INSTRUMENTS
Software ...


          TEXAS INSTRUMENTS
Software Framework for a Digital Controller

   “infrastructure which supports the application”

  Considerations
      How many ISRs (Interrupt Service Routines)
      Are ISRs Synchronous or Asynchronous ?
      CPU % utilization balance between ISRs and Background (BG)
      High level language (HLL), e.g. “C/C++”, Assembly ?, or both ?
      Need to employ an Operating system ?
      Interrupt driven Communications ?




                                                             TEXAS INSTRUMENTS
The simple “ISR / BG” Framework                                (1/2)


                  “keep it simple”
  BG loop

            ISR

                   Context Save    2 Loops only
                                   ISR code has highest priority
                                   ISR Synchronous to PWM switching
                                   ISR incurs entry/exit overhead
                                   BG runs only during ISR “idle time”
                      ISR body




                     Context
                     Restore




                                                         TEXAS INSTRUMENTS
   The simple “ISR / BG” Framework                                                             (2/2)




PWM

         Interrupt                                                                                     t
                            idle                 idle
 ISR     base        TS1   time    base   TS2   time    base     TS3        base   TS4          base

 Back
Ground
                           BG                   BG                     BG                 BG
                                                          Time-slice
                 Tsample




        Can Time slice the ISR for simple synchronous multi-task scheduling
        In a practical system BG needs approx 15~20% of CPU bandwidth
        If CPU timing is “tight” may consider using a H/W accelerated controller




                                                                                         TEXAS INSTRUMENTS
                Single ISR / BG loop example

             Main
                                                                 ISR        400 KHz


         Initialisation

    Device level (CPU, PLL,..)                           Execute every ISR call
 Peripheral level (ADC, PWM...)                            fast Vloop or ILoop

  System level (GPIO, Comms)
                                                                             Time Slice
     Framework (BG / ISR)                                                     manager
           Interrupts

                                     100 KHz   100 KHz                            100 KHz    100 KHz


     Background loop               TS1               TS2                      TS3                TS4
                                  loop1             loop2                  filtering            OVP mgr
Startup / Shutdown / sequencing
           Margining
Diagnostics / Reporting / Comms
       Fault management
       Slow control loops                                        Return




                                                                                          TEXAS INSTRUMENTS
  Time Sliced ISR – Practical example                                                                   (1/2)

 Interrupt    TS1                        TS2                   TS3                   TS4               TS1      t
 ISR     I V I V                  I V     I     I          I V I V   1/        I V    I               I V I
                                                                                           RA
(200KHz) 1 1 2 2                  1 1    Pfc   bal         1 1 2 2   x2        1 1   cmd              1 1 2

  Back                    B                          B                     B                      B
 Ground                   G                          G                     G                      G

             5000 nS

                 Code Function                 PWM rate         Code execution         Identifier
                                                (KHz)            rate (KHz)
                 DC/DC-1 V Loop                      200             200                   V1
                  DC/DC-1 I Loop                     200             200                    I1
                 DC/DC-2 V Loop                      200             100                   V2
                  DC/DC-2 I Loop                     200             100                    I2
                     PFC I loop                      100              50                   IPfc
              PFC V loop (done in BG)                                 50                   VPfc
              PFC 1/X2 (X=Vac Rect &                                  50                   1/X2
                       Avg)
              PFC I-cmd (V1*V2*V3)                                    50                   Icmd
             PFC Vac Rect. and Average                                50                   RA
                    PFC I-balance                                     50                   Ibal

                                                                                                  TEXAS INSTRUMENTS
     Time Sliced ISR – Practical example                                                                              (2/2)


  Interrupt         TS1                      TS2                      TS3                   TS4                  TS1       t
  ISR
              B1    B2     B3        B1      B2    B4          B1    B2      B5       B1    B2    spare        B1     B2   B3
(600KHz)


  Back                           B                        B                       B                       B
 Ground                          G                        G                       G                       G

                   1667 nS



                   Code Function                    PWM rate (KHz)            Code execution rate             Identifier
                                                                                    (KHz)
              Buck 1 - single phase V Loop                    600                     600                        B1

              Buck 2 - single phase V Loop                    600                     600                        B2

              Buck 3 - 4-phase IL V Loop           300 / phase (90o apart)            150                        B3

              Buck 4 - 3-phase IL V Loop          300 / phase (120o apart)            150                        B4

              Buck 5 - 3-phase IL V Loop          300 / phase (120o apart)            150                        B5




                                                                                                          TEXAS INSTRUMENTS
     Hardware Accelerated Controllers                                         (1/2)


  F280x                                     UCD9110

                             Ch1                                                   Ch1
   DSP          ADC          Ch2              MCU               ADC                Ch2
 32 bit core
                12 bit                      16 bit core         12 bit
  50~100
                (80nS)                        4 MHz             (5 uS)
    MHz
                             Ch16                                                  Ch8



                             PWM1A
                                     EA+                                           PWM1A
               DPWM1                        EADC          CLA      DPWM1
                             PWM1B
                                     EA-                                           PWM1B
                             PWM2A
               DPWM2                                                               PWM2A
                             PWM2B          Error ADC              DPWM2
                                               5 bit                               PWM2B
                             PWM3A          (~300 nS)
               DPWM3
                             PWM3B



                                              Accelerated Controller
                             PWM8A
               DPWM8
                             PWM8B


                                           Note: CLA = Control Law Accelerator
Non-Accelerated Controller



                                                                         TEXAS INSTRUMENTS
            Hardware Accelerated Controllers                                                                                 (2/2)

Interrupt                                                                                                     t
                                      TC1

CLA1        C1 C1 C1 C1 C1 C1 C1 C1 C1 C1 C1 C1 C1 C1 C1 C1 C1 C1 C1 C1 C1
                                                                                                                   UCD9110 example
                                                                                                                       with CLA
 ISR             C2              C3                              C2             C3                           C2
                                                                                                                   Note: a 3 execution
 Back-
ground
                                                 BG                                            BG                    thread system.
                           Tsample




Interrupt                                                                                                     t
 ISR        C1    C2             C1                   C1   C3             C1                  C1    C2             F2801 example #1
                                                                                                                  Time-sliced ISR for
 Back-
ground
                         BG                 BG                    BG              BG                               slow loops C2, C3
                 TC1


Interrupt                                                                                                     t
 ISR        C1                   C1                   C1                  C1                  C1                  F2801 example #2
 Back-
                                                                                                                  BG managed slow
                  C2 / C3 / BG        C2 / C3 / BG         C2 / C3 / BG        C2 / C3 / BG
ground                                                                                         C2, C3 rate
                                                                                                                    loops C2, C3
                                                                                               scheduled
                  TC1                                                                          by BG code




                                                                                                                      TEXAS INSTRUMENTS
           Code development strategy

 Modularity - blocks with well defined inputs / outputs
   (“cause and effect”)
 Multiple Instancing - use of same function (module) many times
 Peripheral (h/w) drivers - separate core code from peripheral code
 Re-useable / Re-targetable - maximize return on investment
 Efficiency & high performance - code execution in minimal time




                                                       TEXAS INSTRUMENTS
                   Software Library approach
                                                       E
     CNTL                 CNTL                BUCK     P
                                                                         HR      E
                                                                                 P
     2P2Z                 3P3Z                                          BUCK
                                               DRV     W                         W
Ref                  Ref                               M                 DRV     M
         Uout                     Uout
 FB                   FB                                   EPWMnA
                                              Duty     H                Duty     H   EPWMnA
                                                       W   EPWMnB                W


IIR-FILT             IIR-FILT
  2P2Z                 3P3Z
                                                           EPWM1A        MPIL        EPWM1A
                                               MPIL    E                         E
                                                       P   EPWM1B        BAL     P   EPWM1B
                                               DRV
              f                     f
                                                       W
                                                           EPWM2A        DRV     W
                                                                                     EPWM2A
                                                       M                         M
                                                           EPWM2B                    EPWM2B
In           Out     In            Out                 H                Duty     H
                                              Duty     W                         W
                                                                        BalAdj

SinGen1              SGenHP1
                                                       E                 PFC     E
                                               HHB     P                         P
                                                                        2PHIL
Freq                 Freq                      DRV     W                         W
                                                       M                 DRV     M
Gain         Out     Gain          Out
                                                           EPWMnA       Duty         EPWMnA
Offset               Offset                   Duty     H                         H
                                                       W   EPWMnB       Adj      W   EPWMnB


 INV                 SLEW
 SQR
                     LIMIT                     ZVS                       PWM     E
                                                       E
                     In                         FB     P   EPWMnA        DAC     P
                            Out
In     Out           Incr                      DRV     W                 DRV     W
                                                           EPWMnB                M
                                                       M
                                              Phase
                                                           EPWM(n+1)A   In1      H   EPWMnA
                                              Llegdb   H
RampGen              SSartSEQ                          W   EPWM(n+1)B
                                                                        In2      W   EPWMnB
                                              Rlegdb


Freq
                                                       A     Ch0
Gain         Out     Delay                     ADC     D     Ch1
                                                             Ch3
Offset               Slope              Out    DRV     C
                                                             Ch4
                     Target
                                                       H
                                              Rslt     W



                                                                                 TEXAS INSTRUMENTS
                     Modular s/w architecture
“Signal Net” based module connectivity
                     f1
     Net1
              In1A
                      Out1       Net5
                                          In4A
                                                 f4
     Net2     In1B               Net6                    Net8
                                          In4B    Out4
                                 Net7
                                          In4C
                     f2
              In2A    Out2
                                                 f5
     Net3



                                          In5A    Out5   Net9

                     f3
     Net4
              In3A    Out3



Initialization time (“C”)                                 Run time (ASM macros)
// pointer & Net declarations                             ; Execute the code
Int *In1A, *In1B, *Out1, *In2A,...
Int Net1, Net2, Net3, Net4,...                                     f1
                                                                   f2
// “connect” the modules
In1A=&Net1; In1B=&Net2; Out1=&Net5;
                                                                   f3
In2A=&Net3; Out2=&Net6;                                            f4
In3A=&Net4; Out3=&Net7;                                            f5
In4A=&Net5; In4B=&Net6; In4C=&Net7; Out4=&Net8;
In5A=&Net7; Out5=&Net9;

                                                                        TEXAS INSTRUMENTS
                PFC (2PHIL) Software control flow
                              VpfcSetSlewed            VpfcCntl                 VpfcOvp
                     1 KHz                                                                                                                                    100 KHz
                                        1 KHz                     100 KHz                 100 KHz
                       SLEW               CNTL                         PFC                     PFC                           100 KHz                              PFC
                       LIMIT              2P2Z                         OVP                    ICMD                                  CNTL                         2PHIL      E   T2PWM
385 V      VpfcSet    In     Out        Ref                                                                                         2P2Z                          DRV       V
                                                Out                In     Out              V1
     VpfcSlewRate     Incr               Fdbk                                                      Out        PfcIcmd          Ref                                          H
                                                                   Vmon                    V2                                         Out         PfcDuty       Duty
                                                                                                                               Fdbk                                         W
                                         Voltage                                                                                                                                T4PWM
 2                                                                                                                                                               Adj
                                        Controller                                        Vac
                                                                                                                                Current
                     Vboost                                                                                                    Controller
                                                              Vboost
                                                                                                                                            PfcShareAdj
 VpfcSet
                                                InvVavgSqr                                           Ipfc
 385 V

                                      50 KHz                      50 KHz                  200 KHz                  200 KHz                                     200 KHz
 160 V                                                                                         AC                       FILT                     Ipfc           rslt0               IN0
                                         INV                         FILT
                                                                   BIQUAD                     LINE                      2P2Z
                                         SQR                                                                                                         Vboost    rslt1                IN1
                                                                                              RECT                                                                       ADC    A
         50mS                                                                                                                                                                   D
                                       Out      In                 Out     In              Out      In                 Out     In               VacLine        rslt2     SEQ1       IN2
                                                                                                                                                                                C
                                                                                                                                                                         DRV
                     Vavg                                                                                                                                      rslt3                IN3
                                                              VacLineAvg        VacLineRect              VacLineFilt                                                            H
                                                                                                                                                               rslt4            W
                                                                                                                                                                                    IN4
                                                                                                                 BOX         50 KHz                            rslt5                IN5
                                                     IphA                                                        CAR
                                                                                                                 AVG
                                                                       100 Hz
                                                                                                 IpfcAvgA       Out     In             IpfcPhaseA
                                                                           PFC                                                                                   HalfVref
                                                                         ISHARE                                  BOX         50 KHz
                                                                                                                 CAR
                                                                                Ia
                                                PfcShareAdj             Out                                      AVG
                                                                                Ib               IpfcAvgB       Out     In             IpfcPhaseB

                                                     IphB



                                                                                                                                                              TEXAS INSTRUMENTS
                  DC-DC (PSFB) Software control flow
                                                                                                                   “ON”             DCDC_Enable        GPIO
                                                                                                                                                   G
                                                                                                                                                   P
                                                                                                                      200 KHz
                                                                                                                                                   I
                           200 KHz                                                                                         ZVS              PWM1   O   PWM1

                            SLEW        VoutSetSlewed
                                                        200 KHz
                                                          CNTL        Voltage      200 KHz                                  FB              PWM2   C   PWM2
                            LIMIT                         2P2Z       Controller    I_FOLD                                  DRV                     N
                                                                                    BACK                                                    PWM7   T   PWM7
 48 V       VoutSet         In    Out                   Ref                                                                phase                   L
                                                               Out       VdcCntl   V     Out       ZvsPhaseCntl                        E               PWM8
                           Incr                                                                                                             PWM8
   2        VoutSlewRate                Vout            Fdbk                        I                                                  V
                                                                                   Rv                                     50KHz
                                                                                                                                       H
VoutSet                                                                            Fv                                       ZVS        W
  48 V                                                                             Ri                                       DB
                                                                                    Fi                                      DRV
                                                          CNTL                           200 nS      ZvsDbAdjL             llegdb
   0V
                                                          2P2Z                           180 nS      ZvsDbAdjR             rlegdb
          100mS            12 A          IoutSet        Ref    Out      IdcCntl
                                               Ipri     Fdbk
                                                                   200 KHz                                    200 KHz
                                                        Current Controller
                                                                                                                                       A
                           Ipri                                                                   Ipri            rslt0
                                                                                                                           ADC         D     IN0

                                                                                                                           SEQ2        C

                           Vout                                                                   Vout            rslt1    DRV         H
                                                                                                                                             IN1
                                                                                                                                       W




                                                                                                                                           TEXAS INSTRUMENTS
                   Multi-output DC s/w management
Start / Stop trigger
                                                                                 Single Power Stage
                                 Voltage                            E

S-start / SEQ                   Controller                BUCK      P            Vin                              Vout1
                                                                    W
                                     CNTL
                                                           DRV      M
                                     2P2Z
                       Vref1                                        H
                               Ref      Uout   DutyCmd1   Duty      W   EPWM1A         DRV              Buck
                               FB
                                                          400 KHz
                               1 MHz
                                                                    A
                                                            ADC     D
                                                            DRV     C

                                                                    H
                                                 Vout1    rslt0     W     Ch0
                                                          400 KHz


                                                                                 Single Power Stage
                                 Voltage                            E

S-start / SEQ                   Controller                BUCK      P            Vin                              Vout2
                                                                    W
                                     CNTL
                                                           DRV      M
                                     2P2Z
                       Vref2                                        H
                               Ref      Uout   DutyCmd2   Duty      W   EPWM1A         DRV              Buck
                               FB
                                                          400 KHz
                               1 MHz
                                                                    A
                                                            ADC     D
                                                            DRV     C

                                                                    H
                                                 Vout2    rslt0     W     Ch1
                                                          400 KHz




                                                                                                      TEXAS INSTRUMENTS
Soft-start & Sequencing multi Vout




                              TEXAS INSTRUMENTS
                       Multi-Phase IL s/w management
                                   +/-   Adj   1
                                   +/-   Adj   2
                                   +/-   Adj   3                                   EPWM4A                          4                                      Vout
Start / Stop trigger               +/-   Adj   4                MPIL        E
                                                                DRV         P
                                                                                   EPWM3A                      3
                                                                            W      EPWM2A                  2
                                  400 KHz
S-start / SEQ                                                               M                                      Vin
                                        CNTL                   DutyAdj
                                                                            H
                                        2P2Z                                W
                       Vref       Ref        Uout              Duty                EPWM1A                  1           GATE
                                                                                                                       DRV
                                  FB
                                                               400 KHz
                                    Voltage
                                   Controller
                                                                 ADC        A
                                                                 DRV
                                                                            D          Ch4                                        I1
                                                                            C          Ch3                                             I2
                                                                                       Ch2                                                  I3
                                               Vout            rslt0        H          Ch1                                                       I4
                                                                            W          Ch0

                                                               400 KHz


                              0                    1             2                 3                   0               1      2    3                  0
                                         D             + % Adj
                       Ph1

                                                           D             - % Adj
                       Ph2

                                                                            D                + % Adj
                       Ph3

                                                                                               D           Zero Adj
                       Ph4

                                                       F



                                                                                                                                  TEXAS INSTRUMENTS
  Multi-output control s/w module
                               C / C++                    Assembly

                                                           N-BuckLoop control module
                                                               Coef[1]
                                                                           2 pole /                DPWM
  Coefficient B2          Coef[1]                               Vref[1]    2 Zero                  module
                                                                                         Uout[1]
  Coefficient B1                                                          Ref    Uout              Duty PWM   PWM-1
                                                                          FB
  Coefficient B0
                                                                          Controller 1              ADC
  Coefficient A2                                                                                   module     ADC-1
  Coefficient A1                                                                                   Out   In

      Dmax                                                     Coef[2]
                                                                           2 pole /                DPWM
      Dmin
                                                                Vref[2]    2 Zero                  module
                                                      N                                  Uout[2]
Coefficient set 1A                       Coef [1-N]                       Ref    Uout              Duty PWM   PWM-2
                                                                          FB

                                                                          Controller 2              ADC
  Coefficient B2
                       Coef[1]
                                                      N                                            module     ADC-2
                                         Vref [1-N]
  Coefficient B1                                                                                   Out   In

  Coefficient B0
                                                      N
  Coefficient A2                         Uout [1-N]
  Coefficient A1
      Dmax                                                     Coef[N]
                                                                           2 pole /                DPWM
      Dmin
                                                               Vref[N]     2 Zero                  module
                                                                                         Uout[N]
                                                                          Ref    Uout              Duty PWM   PWM-N
Coefficient set 1B
                                                                          FB

                                                                          Controller N              ADC
  S-start / SEQ                                                                                    module     ADC-N
                                                                                                   Out   In
                     Vref[1]




                                                                                                    TEXAS INSTRUMENTS
                     How many Vreg outputs ?
CPU speed (MHz)               100         Control loop (cyc)       27            CPU prd (nS)    10.0
Context save (cyc)            12          Misc Mgmt                4
Context restore (cyc)         12          Background code (cyc)    300

# DC/DC loops                       200       300          400           500         700         1000     KHz
                                    5.0       3.3          2.5           2.0         1.4          1.0     uS
         1
     Overhead
    Control laws        28
                        27     11.0%
                                5.6%
                                5.4%        16.5%
                                             8.4%
                                             8.1%        22.0%
                                                          11.2%
                                                          10.8%     27.5%
                                                                     14.0%
                                                                     13.5%         38.5%
                                                                                    19.6%
                                                                                    18.9%       55.0%
                                                                                                 28.0%
                                                                                                 27.0%
  BG spare (MIPs)               89.0          83.5         78.0      72.5           61.5         45.0
 BG loop spd (KHz)              296.7         278.3        260.0     241.7          205.0        150.0

         2
     Overhead
    Control laws        28
                        54     16.4%
                                 5.6%
                                10.8%       24.6%
                                             8.4%
                                             16.2%       32.8%
                                                          11.2%
                                                          21.6%     41.0%
                                                                     14.0%
                                                                     27.0%         57.4%
                                                                                    19.6%
                                                                                    37.8%       82.0%
                                                                                                 28.0%
                                                                                                 54.0%
  BG spare (MIPs)               83.6          75.4         67.2      59.0           42.6          18.0
 BG loop spd (KHz)              278.7         251.3        224.0     196.7          142.0         60.0

         3
     Overhead
    Control laws        28
                        81     21.8%
                                 5.6%
                                16.2%       32.7%
                                             8.4%
                                             24.3%       43.6%
                                                          11.2%
                                                          32.4%     54.5%
                                                                     14.0%
                                                                     40.5%         76.3%
                                                                                    19.6%
                                                                                    56.7%       109.0%
                                                                                                 28.0%
                                                                                                 81.0%
  BG spare (MIPs)               78.2          67.3         56.4      45.5            23.7         -9.0
 BG loop spd (KHz)              260.7         224.3        188.0     151.7           79.0        -30.0

         4
     Overhead
    Control laws        28
                        108    27.2%
                                 5.6%
                                21.6%       40.8%
                                             8.4%
                                             32.4%       54.4%
                                                          11.2%
                                                          43.2%     68.0%
                                                                     14.0%
                                                                     54.0%         95.2%
                                                                                    19.6%
                                                                                    75.6%       136.0%
                                                                                                 28.0%
                                                                                                 108.0%
  BG spare (MIPs)               72.8          59.2         45.6      32.0            4.8          -36.0
 BG loop spd (KHz)              242.7         197.3        152.0     106.7           16.0        -120.0

         5
     Overhead
    Control laws        28
                        135    32.6%
                                 5.6%
                                27.0%       48.9%
                                             8.4%
                                             40.5%       65.2%
                                                          11.2%
                                                          54.0%     81.5%
                                                                     14.0%
                                                                     67.5%        114.1%
                                                                                   19.6%
                                                                                   94.5%        163.0%
                                                                                                 28.0%
                                                                                                 135.0%
  BG spare (MIPs)               67.4          51.1         34.8          18.5       -14.1         -63.0
 BG loop spd (KHz)              224.7         170.3        116.0         61.7       -47.0        -210.0

         6
     Overhead
    Control laws        28
                        162    38.0%
                                 5.6%
                                32.4%       57.0%
                                             8.4%
                                             48.6%       76.0%
                                                          11.2%
                                                          64.8%     95.0%
                                                                     14.0%
                                                                     81.0%        133.0%
                                                                                   19.6%
                                                                                   113.4%       190.0%
                                                                                                 28.0%
                                                                                                 162.0%
  BG spare (MIPs)               62.0          43.0         24.0          5.0         -33.0        -90.0
 BG loop spd (KHz)              206.7         143.3        80.0          16.7       -110.0       -300.0

         7
     Overhead
    Control laws        28
                        189    43.4%
                                 5.6%
                                37.8%       65.1%
                                             8.4%
                                             56.7%       86.8%
                                                          11.2%
                                                          75.6%    108.5%
                                                                    14.0%
                                                                    94.5%         151.9%
                                                                                   19.6%
                                                                                   132.3%       217.0%
                                                                                                 28.0%
                                                                                                 189.0%
  BG spare (MIPs)               56.6          34.9         13.2           -8.5       -51.9       -117.0
 BG loop spd (KHz)              188.7         116.3        44.0          -28.3      -173.0       -390.0

         8
     Overhead
    Control laws        28
                        216    48.8%
                                 5.6%
                                43.2%       73.2%
                                             8.4%
                                             64.8%       97.6%
                                                          11.2%
                                                          86.4%    122.0%
                                                                     14.0%
                                                                    108.0%        170.8%
                                                                                   19.6%
                                                                                   151.2%       244.0%
                                                                                                 28.0%
                                                                                                 216.0%
  BG spare (MIPs)               51.2          26.8          2.4          -22.0       -70.8       -144.0
 BG loop spd (KHz)              170.7         89.3          8.0          -73.3      -236.0       -480.0


                                                                                             TEXAS INSTRUMENTS
 Power Supply
Control Loop...

            TEXAS INSTRUMENTS
Introduction
   • Analog control of Power Supply
   • Digital control of Power Supply
   • Design by Emulation (DBE)
   • Direct Digital Design (DDD)
   • Design Example



                              TEXAS INSTRUMENTS
              Analog Control of Power Supply
                                    e       EA           u                      d      P
                 r +                    (volt/current       PWM                      (power
                                                                                                     y
                               -
            (reference)                    error amp                                               (volt/
                                                                                    converter)
                                        compensation)                                             current)

“analog computation”
                           Ky
 s-domain equations                                                K
                                                             (feedback)
                               C2
                                                                                            C
                      C1
                                                                       y
                                               R
                                                                                       Q           Switching &
                               R2                                          R3
                                                              Ky                            RL
                                        R                                                             output
                      R1
                                                                                                   filter stage
                                                                       R4                   L


     EA gain or
  analog controller
                                                                                                    Y
                       U R  1  R1C1s 
               C ( s)   2                                                              P( s ) 
                       E R1  s(1  R2C2 s) 
                                                                                                  d
                                                                                Power stage ss model
               Need to find :
               R 1, R 2 , C 1, C 2

                                                                                                   TEXAS INSTRUMENTS
         Digital Control of Power Supply
                            e[n]          Cd           u[n]                d         P
        r[n]
                 +                   (controller)
                                                                 DPWM              (plant)               y
                          -Ky[n]
                                                   A-D                 K
Difference equation
                                               S+ZOH+Quantizer



                                                                               C


               U (n)  a2  U (n  2)  a1  U (n  1)                                      Switching &
                                                                               R
                                                                           Q                 Output filter
                        b2  E (n  2)  b1  E (n  1)  b0  E (n)                            stage
                             where E(n)  R(n)  KY(n)
                                                                              L




                                                                       Power stage ss model P(s)
           Need to find:
           a1, a2, b0, b1, b2
                                                                       Z Transform


                                                                                                TEXAS INSTRUMENTS
                Design by Emulation (DBE)
                           e         Cd           u     PWM d             P
        r
               +                (controller)                           (plant)             y
                       -
                                                A-D               K



    Ignore S/H effect, choose controller type (PID, lag, lead, 2p-2z)
1   Derive Plant model  P(s)

    Closed loop gain                      Y (s)     Cd ( s ) P ( s )
2                              H ( s)          
                                          R( s ) 1  KCd ( s ) P( s )

3   Use Bode plot and system criteria (BW, PM, GM) to design analog controller Cd(s).

                                                                                 2  1  z 1 
4   Transform Cd(s) to Cd(z)  use: Tustin bilinear transform:                      1  z 1 
                                                                              s            
                                                                                 T           
5   Transform Cd(z) to difference equation  use:              x(n-1) ↔ z -1. X(z)


                                                                                         TEXAS INSTRUMENTS
                 Direct Digital Design (DDD)

                         E       Cd           U       Hc                        P
    R
            +               (controller)
                                                      Comp
                                                      delay
                                                                  DPWM
                                                                              (plant)         W
                     -
                                                                      A-D
                                                                      S+ZOH    K
                                                                                          “Digital Plant”

1   Choose controller type, e.g. 2p-2z, 2p-1z

    Digitize Plant model P(s)  P(z) use: P(z) = Z{ P(s) . ZOH(s) . Hc }
2
    this exactly accounts for ZOH + Computation delay.

    Closed loop gain                    W ( z)    Cd ( z ) P ( z )
3                            H ( z)           
                                        R( z ) 1  KCd ( z ) P( z )


4   Design Cd(z) to meet system criteria.  use: Z-Domain Root locus, Bode plot,


5   Transform Cd(z) to difference equation  use:             x(n-1) ↔ z -1. X(z)


                                                                                        TEXAS INSTRUMENTS
Design Example
  • Digital control - DC/DC conv.
  • Sampling scheme
  • Design by Emulation (DBE)
  • Direct Digital Design (DDD)




                               TEXAS INSTRUMENTS
Digital Control of DC/DC Converter

         Iin                              Io    Vo
                           L
  Vin                                 C          RL



         Vin = 4V ~ 6V,
         Vo = 1.6V, Io = 16A
         L = 1uH, C = 1620uF, ESR = 0.004 ohm
         PWM Freq = 250kHz,
         Digital Control Loop Sampling Freq, fs = 250kHz,
         Voltage Control Loop Bandwidth = 20kHz,
         Phase Margin = 45 deg
         Settling Time < 75uSec


                                                        TEXAS INSTRUMENTS
           Design by Emulation (DBE)

               Iin                                                    Kd
                                                    Vo
                               L
     Vin                                 C               Vos
                                               RL




                      d                                    A/D
                         PWM
          Vo                                         Vo(n)
G P (s) 
                               U(n)
          d                            Gc(z)                   +
                                                      E(n)
                     UCD9508                        Vref




                                                                   TEXAS INSTRUMENTS
      Calculating Gp(s) – continuous plant
Ignore Sample & Hold (S&H) Effect,
PWM Modulator Gain Fm = 1,                         G1p(s)
Continuous Plant Gp1(s) = Kd.Fm.Gp(s)                 d               Vo
                                                             Gp(s)
 Vin=5.0, RL=0.1, Kd=0.5,
 L=1uH, C=1620uF, Rc=0.004 ohm,                     Fm                  Kd


             1.62x10-5 s + 2.5                                       Vo(n)
Gp1(s) = ---------------------------------------      U(n)
                                                             Gc(z)
                                                                     E(n)
                                                                             +
           1.685x10-9 s2 + 1.648x10-5 s + 1
                                                                 Vref
Need to find:
     Gc(s) = ? - use Root locus, Bode, ... other
     Gc(z) = ?

                                                              TEXAS INSTRUMENTS
  Equivalent Discrete controller Gc(z)
 1. Discrete Equivalents via Numerical Integration
                     a) Forward rule, s= (z-1)/Ts
                b) Backward rule, s = (z-1)/zTs
                c) Trapezoidal/Tustin/Bilinear, s = 2(z-1)/Ts(z+1)
 2. Pole-Zero Matching Equivalents, z = esTs
 3. Hold Equivalents : zero-order-hold (ZOH), first-order-hold (FOH)

E.g. 1) In Matlab, Gc_z = c2d(Gc_s, Ts, 'matched')
           12.34 z^2 - 22.53 z + 10.28
                                                        [pole-zero matched,
Gc1(z) = -------------------------------------------
                                                     Ts = 4uSec, i.e. 250KHz]
           z^2 - 1.605 z + 0.6051
E.g. 2) In Matlab, Gc_z = c2d(Gc_s, Ts, „tustin')
           12.49 z^2 - 22.81 z + 10.41
Gc1(z) = ------------------------------------       [Tustin, Ts = 4uSec]
           z^2 - 1.598 z + 0.5985


                                                                 TEXAS INSTRUMENTS
     Transient response result
(Fpwm = 250KHz), pole-Zero Matched
Controller




                                     Gp1(z)*Gc1(z)




                                       TEXAS INSTRUMENTS
          Direct Digital Design (DDD)
               Iin                                   Vo
                                 L
         Vin                             C
                                             RL
                                                          Kd


                                                          Ts

                       d                                  ZOH
                           DPWM
                                                    Vo(n)
          Vo                                          E(n)
G P (s)                             Hc U(n) Gc(z)
                                                              +

          d
Comp Delay Model       UCD9508                    Vref
Hc = e-sTd ,
Td = Computational Time Delay
                                                             TEXAS INSTRUMENTS
                     Sampling Scheme                           (1 of 4)

Sample to PWM Update Delay Td = 2Ts (Computation Delay)

                     N                            N+1                   N+2
                                       Ts    (Sample period)


          CTR = Zero
  CTR

                                                                                           t

  PWM                               PWM
                                   update

         INT


  CPU          ISR        BG                ISR           BG      ISR         BG     ISR



               SW
  ADC          SOC

                                 Td
                         (computation delay)

                                                                              TEXAS INSTRUMENTS
                   Sampling Scheme                                    (2 of 4)

Computation Delay: Td ~ 0.75Ts i.e. 0.5Ts ≤ Td ≤ 1Ts
                       N                             N+1                        N+2
                                             Ts   (Sample period)


               CTR = duty/2
   CTR


                                     PWM
                                                                                                      t
                                    update


   PWM

          HW SOC
   ADC
                 INT


   CPU   ISR     BG        TC
                                   ISR       BG       TC        ISR   BG   TC         ISR     BG

                              Td                           Td                    Td
                   (computation delay)

                                                                                            TEXAS INSTRUMENTS
               Sampling Scheme                                    (3 of 4)

Computation Delay: Td = 0.5Ts
                    N                            N+1                    N+2
                                         Ts   (Sample period)
              CTR=PRD


  CTR

                                                                                          t
                               PWM
  PWM                         update



          HW SOC

  ADC
                   INT


  CPU   ISR   BG         TC
                                 ISR           BG       TC
                                                                ISR    BG     TC
                                                                                   ISR

                           Td
                   (computation delay)

                                                                               TEXAS INSTRUMENTS
                 Sampling Scheme                                           (4 of 4)

Computation Delay: Td ≤ 0.5Ts
                    N                                  N+1                        N+2
                                              Ts    (Sample period)
          CTR = fixed value


   CTR


                                      PWM
                                                                                                      t
                                     update


   PWM

                  HW SOC
   ADC
                          INT


   CPU    ISR           BG       TC
                                              ISR          BG         TC
                                                                            ISR     BG     TC
                                                                                                ISR

                                Td
                      (computation delay)

                                                                                         TEXAS INSTRUMENTS
Effect of Sample and Hold

                        Time Delay Ts/2




                                  Ts
  PM = 33.18 deg

                            ZOH = -ωTs/2
                               = -180f/fs



                         fs = 250kHz,
                          f = 7.25kHz,
                           additional
                        phase lag of 5.2°


    PM = 28 deg                f = 125kHz,
                                additional
                             phase lag of 90°


                            TEXAS INSTRUMENTS
        Calculating Gp(z) – discrete plant
Vin=5.0, RL=0.1, Kd=0.5                                         Gp1(z)
L=1uH, C=1620uF,
Rc=0.004 ohm                                                       d                Vo
                                                                          Gp(s)
            1.62x10-5 s + 2.5                                   PWM
                                                                                         Kd
Kd.Gp(s) = -------------------------------------                                    Ts
          1.685x10-9 s2 + 1.648x10-5 s + 1
                                                                  Hc
                                                                                    ZOH
ZOH(s) = (1 – e-sTs )/s           accounts for sample & hold
                                        + comp. delay
Hc = e-sTd                                                                        Vo(n)
                                                                  U(n)            E(n)
Discrete Plant Model,                                                    Gc(z)            +

Gp(z) = Z{ZOH(s).Kd.Gp(s).Hc}                                                     Vref
Gp1(z) = (0.0494z - 0.0261)/(z2 - 1.952 z + 0.962), [Td=0, Hc = 1]
          Note: for now use Td = 0, as a base line comparison

                                                                         TEXAS INSTRUMENTS
     Calculating Gc(z) – using Matlab
Use Matlab SISOTOOL for Gp1(z), and design Gc2(z)

                                     Discrete System Bode Plot,
                                     2 Pole 2 Zero Type Controller,
                                                                      Gp1(z)*Gc2(z)
                                                                        (Td=0)
                          BW = 27.9kHz, PM = 61.6 deg, GM = 9dB




                                                                  Gp(z)      Vo(n)
            14.87 z^2 - 26.91 z + 12.16
 Gc2(z) = -------------------------------------            U(n)              E(n)
                                                                   Gc(z)             +
            z^2 - 1.473 z + 0.4731
                                                                            Vref
                                                                          TEXAS INSTRUMENTS
Effect of Computational delay - [Td = 0.5Ts]
 Plant: with computation delay [Td = 0.5Ts],
 Gp2(z) = (0.022z^2+0.017z - 0.158)/z(z^2 - 1.952 z + 0.962),
 Controller with no delay compensation,
 Gc2(z)=(14.87 z^2 - 26.91 z + 12.16)/(z^2 - 1.473 z + 0.4731 )

                                                                  Phase Lag,
                                      Gp2(z)*Gc2(z)               Hc = -ωTd
                                                                         =-
                                                                    360fTd
                                                            Loss of PM from
                                                           (Gp1*Gc2) to (Gp2*Gc2)
                                                                = 61.6-41
                                                                = 20.6 deg

             BW = 26.9kHz, PM = 41 deg, GM = 7.46dB         Hc = 360(26900)(2uS)
                                                               = 19.37 deg




                                                                   TEXAS INSTRUMENTS
Transient response result (FPWM=250KHz)




                                Gp2(z)*Gc2(z)




                                TEXAS INSTRUMENTS
                     Control Law realization                                                  1 of 2




                   14.9 z2 – 26.9 z + 12.2                14.9 – 26.9 z -1 + 12.2 z -2
 Gc(z) = U / E = ------------------------------------ = -----------------------------------
                    z2 - 1.47 z + 0.47                    1 – 1.47 z -1 + 0.47 z -2

  14.9 E(z) – 26.9 z-1 E(z) + 12.2 z-2 E(z) = U(z) – 1.47 z-1 U(z) + 0.47 z-2 U(z)

  U(z) = – z-2{0.47 U(z)} + z-1{1.47 U(z)} + z-2{12.2 E(z)} – z-1{26.9 E(z)} + z-0{14.9 E(z)}

Use: x(n-a) <==> z-a X(z)

  u(n) = – 0.47 u(n-2) + 1.47 u(n-1) + 12.2 e(n-2) – 26.9 e(n-1) + 14.9 e(n)


u(n) = a2*u(n-2) + a1*u(n-1) + b2*e(n-2) – b1*e(n-1) + b0*e(n)

    Where, a2 = – 0.47, a1 = 1.47, b2 = 12.2, b1 = – 26.9, b0 = 14.9



                                                                                   TEXAS INSTRUMENTS
                                 Control Law realization                                                     2 of 2



       u(n) = a2*u(n-2) + a1*u(n-1) + b2*e(n-2) – b1*e(n-1) + b0*e(n)


e(n)
                   Z-1                   Z-1                           IIR (Infinite Impulse Response) Filter
            e(n)                e(n-1)              e(n-2)

       b0                   b1                 b2
                                                                                   b0 – b1*z -1 + b2*z -2
                                                                         U / E = -----------------------------
                                                                                   1 – a1*z -1 + a2*z -2
       +                    +                  +             u(n)      Roots of denominator = Poles
                                                                       Roots of numerator = Zeros

       a2                   a1
             y(n-2)             y(n-1)


                      Z-1                Z-1
                                                             2nd order biquad IIR filter section
                                                             can be used to realize a 2 pole / 2 zero controller



                                                                                                 TEXAS INSTRUMENTS
       Sampling frequency (fs) selection
Design by               Neglect ZOH & Computational delay                 fs ≈ 30 x fc
Emulation (DBE)         “poor sampling strategy”, i.e. Td = 2Ts
                        Neglect ZOH & Computational delay                 fs ≈ 20 x fc
                        “good sampling strategy”, i.e. Td = 0.5Ts
Direct digital          Account for ZOH & Computational delay             fs ≈ 15 x fc
Design (DDD)            “poor sampling strategy”, i.e. Td = 2Ts
                        Account for ZOH & Computational delay             fs ≈ 10 x fc
                        “good sampling strategy”, i.e. Td < 0.5Ts




                 fs = 12.5*fc                                       fs = 20*fc




                                                                                 TEXAS INSTRUMENTS
TEXAS INSTRUMENTS
Spare....




            TEXAS INSTRUMENTS
                                            Module Sync’ing and Phase Control
Single EPWM module
                                                                                                                                                       Ext Sync In
                                                                                                                                                        (optional)
                                                                                                                       Master
Time-Base (TB)
                                                                                Sync                                    Phase Reg       En    SyncIn
 TBPRD Shadow (16)                                        CTR=ZERO             In/Out

                                                                                                                         F
                                                                               Select                 EPWMxSYNCO
 TBPRD Active (16)                                        CTR=CMPB              Mux

                                                          Disabled
                                                                                                                                                         EPWM1A
                                                                               S0 S1
                                 CTR=PRD

                                                                        TBCTL[SYNCOSEL]
                                                                                                                                  CNT=Zero
     16
                                                                                                       EPWMxSYNCI            CNT=CMPB                    EPWM1B
     Counter                                                                  TBCTL[SWFSYNC]
    UP / DWN             TBCTL[CNTLDE]                                      (software forced sync)

     (16 bit)
                                                                                                                         1          X
     TBCNT                  CTR=ZERO
                                                                                                                                             SyncOut
    Active (16)             CTR_Dir



     16

                       Phase
   TBPHS Active (16)                                             CTR=PRD
                       Control
                                                                                                     EPWMxINTn
                                                                CTR=ZERO
                                                                                       Event
                                                                                     Trigger &
                                                                 CTR=CMPA                            EPWMxSOCA
                                                                                     Interrupt
                                                                                        (ET)
Counter Compare (CC)                                             CTR=CMPB

                                                                  CTR_Dir
                                                                                                     EPWMxSOCB
                                                                                                                       Slave
     16                   CTR=CMPA

                                            Action
                                                                                                                        Phase Reg       En   SyncIn
                                                                                                                         F
                                           Qualifier
                                             (AQ)
     16
                                                                                                                                                        EPWM2A

    CMPA Active (16)
                                            EPWMA                                                     EPWMxAO                   CNT=Zero
   CMPA Shadow (16)
                                                       Dead           PWM                Trip                                CNT=CMPB                   EPWM2B
                                                       Band          Chopper             Zone

     16
                                                       (DB)            (PC)              (TZ)
                                                                                                                        2           X
                          CTR=CMPB
                                            EPWMB                                                     EPWMxBO                                SyncOut
     16

    CMPB Active (16)                                          EPWMxTZINTn

   CMPB Shadow (16)                                                                                     TZ1n to TZ6n
                                                          CTR=ZERO




                                                                                                                                                TEXAS INSTRUMENTS
                Phase control with EPWM module
                TBCTR
        FFFFh
                 Master Module
                                          600                        600
TBPRD




         0000

CTR=Zero
(SycnOut)
                                                                                  time
                TBCTR
     FFFFh                           F
                                                Phase = 120o
                Slave Module
                               600                             600
TBPRD

                                          200                        200
TBPHS

         0000


SyncIn

                                                                                  time


                                                                           TEXAS INSTRUMENTS
                                Multi-Phase Interleaved (MPI)                                  1/2
Master                                                  4B
 Phase Reg         En   SyncI                      3B                                                Vout
  F                                      2B
                                EPWM1A
         CNT=Zero
                                                         Vin
     CNT=CMPB                   EPWM1B
 1             X
                        SyncO



Slave                                    1B                    GATE
                                                               DRV

 Phase Reg         En   SyncI
 F                        EPWM2A
         CNT=Zero
     CNT=CMPB                   EPWM2B
 2             X
                        SyncO


                                         EPWM1B
Slave
 Phase Reg         En   SyncI                                     F
           
 F
                                EPWM3A
         CNT=Zero
     CNT=CMPB                   EPWM3B   EPWM2B
 3             X
                        SyncO
                                                                          F

Slave
 Phase Reg         En   SyncI            EPWM3B
           
 F
                                EPWM4A
         CNT=Zero                                                              F
     CNT=CMPB                   EPWM4B
 4             X
                        SyncO
                                         EPWM4B



                                                                                        TEXAS INSTRUMENTS
                                  Multi-Phase Interleaved (MPI)                                                                       2/2

Master                                               Z                                 Z                           Z                           Z
 Phase Reg           En   SyncI
                                                     I                                 I                           I                           I
         
  F
                                  EPWM1A
          CNT=Zero                                             CA   P CA                         CA   P CA                   CA   P CA
     CNT=CMPB                      EPWM1B                           A                                 A                           A
 1               X
                          SyncO             EPWM1A       RED                               RED                         RED




Slave                                       EPWM1B                               FED                         FED                         FED


 Phase Reg           En   SyncI
 F                          EPWM2A                       F
          CNT=Zero
     CNT=CMPB                      EPWM2B
                                            EPWM2A
 2               X
                          SyncO
                                            EPWM2B

Slave
 Phase Reg
                                                                        F
                     En   SyncI
             
 F
                                  EPWM3A
          CNT=Zero
                                            EPWM3A
     CNT=CMPB                      EPWM3B

 3               X                          EPWM3B
                          SyncO


                                                                                 F
Slave
 Phase Reg           En   SyncI
 F
                                  EPWM4A    EPWM4A
          CNT=Zero
     CNT=CMPB                      EPWM4B   EPWM4B
 4               X
                          SyncO




                                                                                                                        TEXAS INSTRUMENTS
                      Multi Channel independent freq.                   1/2


Master
                                         1B
 Phase Reg       En   SyncIn
                                              Vin              Vout1B
  FX
                               EPWM1A                        Vout1A
         CNT=Zero
     CNT=CMPB                  EPWM1B
                                        1A          GATE
                                                    DRV
 1           X
                      SyncO



Master
                                         2B
 Phase Reg       En   SyncIn
                                                               Vout2B
  FX                        EPWM2A
                                              Vin
                                                             Vout2A
         CNT=Zero
     CNT=CMPB                  EPWM2B
             X                          2A          GATE
                                                    DRV
 2                    SyncO



Master
                                         3B
 Phase Reg       En   SyncIn
                                                               Vout3B
  FX                                       Vin
                               EPWM3A
                                                             Vout3A
         CNT=Zero
     CNT=CMPB                  EPWM3B

 3           X                          3A          GATE
                                                    DRV
                      SyncO




                                                           TEXAS INSTRUMENTS
                                Multi Channel “synchronized” freq.
Master            f1
 Phase Reg        En    SyncIn                            4
   F                                              3                                              Vout4
                                 EPWM1A
           CNT=Zero                               2                                               Vout3
      CNT=CMPB                   EPWM1B
                                                              Vin                            Vout2
  1          X
                        SyncO                                                             Vout1

 Slave           2*f1
 Phase Reg        En    SyncIn                1                     GATE
                                                                    DRV
  F*                         EPWM2A
           CNT=Zero
      CNT=CMPB                   EPWM2B
  2          X
                        SyncO                     Master Module
                                                  f1 = 1 / Period
 Slave           4*f1
 Phase Reg        En    SyncIn
  F*
                                 EPWM3A   SyncO

           CNT=Zero                                                        Phase = 0o
      CNT=CMPB                   EPWM3B           Slave Module
  3          X
                        SyncO                     f2 = 2 * f1


 Slave           5*f1
                                                  f3 = 4 * f1
 Phase Reg        En    SyncIn
  F*
                                 EPWM4A
           CNT=Zero
      CNT=CMPB                   EPWM4B           f4 = 5 * f1

  4          X
                        SyncO
* could be constant
  offset


                                                                                        TEXAS INSTRUMENTS
         Configuration example #1

         VIN 1


                          Triple output
VOUT 1
                            o   4-phase interleaved
                            o   Two single phase
                          Single Vin




VOUT 2




VOUT 3




                                        TEXAS INSTRUMENTS
         Configuration example #2

          VIN 1


                           Dual output
VOUT 1
                             o   2 x 3-phase interleaved
                           Single Vin




VOUT 2




                                        TEXAS INSTRUMENTS
         Configuration example #4
          VIN 2

          VIN 1



VOUT 1
                           Six output voltages
                             o   Independent control
                                 loops
VOUT 2
                             o   Individual monitoring
                             o   Adjustable interleaving
VOUT 3
                           Single or dual Vin
                            capable
VOUT 4



VOUT 5



VOUT 6




                                        TEXAS INSTRUMENTS
                                 System Framework
                       5uS                     Time-slice
                      (200KHz)


    ISR   base         TS1            base   TS2            base   TS3        base   TS4        base

 Back
Ground
                                 BG                BG                    BG                BG
          Interrupt                                                                                    t

    Can address the control of most power system (even complex ones)
    Simple to use and understand
    Efficient (incurs only 1 ISR context save/restore)
    Deterministic (all events synchronous and submultiples of ISR freq.)
    High degree of visibility during debug and development
Back-ground loop (BG)
• C / C++, code can be large and complex
• Feature rich e.g. diagnostics, fault management, communications, ….etc
• System intelligence / application‟s personality defined here

Interrupt Service Routine (ISR) – Main control loop
• Low cycle count “in-line” assembly (ASM), this results in a very small footprint.
• Control and “Math function” type code only. “if then else” branches or loops are avoided
• Once developed, should change very little. Low maintenance burden.

                                                                                            TEXAS INSTRUMENTS
                 Sampling Considerations                                            1 of 2



Sample to PWM Update Delay Td = 2Ts (Computation Delay)

                     N                            N+1                N+2
                                       Ts    (Sample period)


          CTR = Zero
  CTR

                                                                                        t

  PWM                               PWM
                                   update

         INT


  CPU          ISR        BG                ISR           BG   ISR         BG     ISR



               SW
  ADC          SOC

                                 Td
                         (computation delay)

                                                                           TEXAS INSTRUMENTS
              Sampling Considerations                                                   2 of 2



Computation Delay: Td = 0.5Ts
                    N                            N+1                   N+2
                                         Ts   (Sample period)
              CTR=PRD


  CTR

                                                                                          t
                               PWM
  PWM                         update



          HW SOC

  ADC
                   INT


  CPU   ISR   BG         TC
                                 ISR           BG       TC
                                                                ISR   BG     TC
                                                                                  ISR

                           Td
                   (computation delay)

                                                                              TEXAS INSTRUMENTS
Digital Power Modules – some examples
Symbol            Descr.        # Cycles    Symbol                            Descr.        # Cycles
     CNTL
     2P2Z                                    PFC
              Controller,                   2PHIL      E
                                                                          PFC 2-phase
                                                               T2PWM
Ref
        Out   2 pole / 2 zero     25         DRV       V                  Interleaved
Fdbk                                                                                          26
                                           Duty        H                  PWM
                                                       W       T4PWM
                                            Adj                           s/w driver
  FILT         IIR
BIQUAD
               digital            23
                                             ZVS                          Zero Voltage
In      Out    filter                         FB               PWM1
                                             DRV
                                                       E
                                                       V
                                                                          Switched
                                                               PWM2
               Inverse                     phase                          Full Bridge         14
     INV                                               H       PWM7
     SQR       square             78       llegdb
                                                       W                  PWM
                                                               PWM8
In      Out    function                    rlegdb                         s/w driver

      PFC
     ICMD      PFC                                               ADC_A0
                                                                          Analog /
V1             Current            30          ADC          A     ADC_A1
                                                                          Digital conv.
        Out                                   SEQ1         D
                                                                 ADC_A2
                                                                                              32
V2             Command                                     C              Sequencer
                                              DRV
                                                                 ADC_A3
Vac            function                                    H              s/w driver
                                                           W     ADC_A4
                                           Rslt[0:5]
                                                                 ADC_A5
 SLEW
               Slew rate
 LIMIT         Limiter            17
In     Out
               function                     MPH3               EPWM1A
Incr
                                                       E                  Multi-phase3
                                             IL        P
                                                               EPWM1B
                                            DRV        W       EPWM2A
                                                                          Interleaved
  PFC
  OVP
               PFC over-                               M
                                                               EPWM2B     PWM                 15
In     Out
               voltage            25       Duty        H
                                                               EPWM3A     s/w driver
                                                       W
Vmon
               monitor                                         EPWM3B



                                                                                          TEXAS INSTRUMENTS
                                    CPU Bandwidth utilization
 MIPS = 100                        # inst / uS = 100      PWM(KHz) = 200
 # TS = 4                  # inst / time slice = 500      PWM(bits) = 9.0                                       FW_Isr          200 KHz
S. rate = 200              Sampling period = 5.0
  ISR      Rate     Function / Activity         # Cyc     Tot. Cyc.     Stats
  All     200KHz Context Save / Restore            32       292         % Util
          200KHz ISR Call / Return / Ack           24                   58%                                Every ISR call
          200KHz Time slice Mgmt                   12                                                         Context Save
          200KHz ADCSEQ2_DRV                       14
                                                                                                             ADCSEQ2_DRV
          200KHz CNTL_2P2Z 1 (V loop)              36
                                                                                                              CNTL_2P2Z(1)
          200KHz CNTL_2P2Z 2 ( I loop)             36
                                                                                                              CNTL_2P2Z(2)
          200KHz   I_FOLD_BACK                     25
                                                                                                               ZVSFB_DRV
          200KHz   ZVSFB_DRV                       14
                                                                                                             ADCSEQ1_DRV
          200KHz   ADCSEQ1_DRV                     57
                                                                                                                FILT_2P2Z
          200KHz   FILT_2P2Z                       35
                                                                                                             AC_LINE_RECT
          200KHz   AC_LINE_RECT                     7

  TS1     100KHz PFC_OVP                           25        117        % Util
          100KHz PFC_ICMD                          30                   82%                                                       Time Slice mgr
          100KHz CNTL_2P2Z 4 (I loop)              36                 #Cyc. Rem.
          100KHz PFC2PHIL_DRV                      26                    91

  TS2     50KHz    BOXCAR_AVG 1                    42        145        % Util
          50KHz    BOXCAR_AVG 2                    42                   87%
          100 Hz   PFC_ISHARE                      15                 #Cyc. Rem.          50 KHz          50 KHz                   50 KHz                50 KHz
          50KHz    Execution Pre-scaler(1:50)      10                    63
           1KHz    CNTL_2P2Z 3 (V loop)            36                                  TS1             TS2                      TS3                   TS4
  TS3     100KHz   PFC_OVP                         25        117        % Util
                                                                                                   BOXCAR_AVG(1)
          100KHz   PFC_ICMD                        30                   82%           PFC_OVP                                  PFC_OVP
                                                                                                   BOXCAR_AVG(2)
          100KHz   CNTL_2P2Z 4 (I loop)            36                 #Cyc. Rem.     PFC_ICMD                                 PFC_ICMD             FILT_BIQUAD
                                                                                                    PFC_ISHARE
          100KHz   PFC2PHIL_DRV                    26                    91         CNTL_2P2Z(4)                             CNTL_2P2Z(4)            INV_SQR
                                                                                                    ExecPS(1:50)
                                                             124                   PFC2PHIL_DRV                             PFC2PHIL_DRV
  TS4     50KHz    FILT_BIQUAD                     46                   % Util                      CNTL_2P2Z(3)
          50KHz    INV_SQR                         78                   83%
                                                                      #Cyc. Rem.
                                                                         84

  BG                Function / Activity         # inst.    Tot.Cyc.     Stats
                   Comms + Supervisory            400        434
                   + Soft-Start + Other ?
                   SLEW_LIMIT 1                    17                                                           Int Ack
                   SLEW_LIMIT 2                    17                                                        Context restore
                                  % ISR utilization =        87%
                                   Spare ISR MIPS =          12.6
                           BG loop rate (KHz) / (uS) =       29.0           34.4                                   Return


                                                                                                                                 TEXAS INSTRUMENTS
The end…...




              TEXAS INSTRUMENTS

								
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