Document Sample

DEPARTAMENT D’ENGINYERIA ELECTRONICA Prediction of Substrate and Switching Noise from High-Level Description of Digital Circuits Doctoral Thesis proposal By: Juan Felipe Osorio jfosorio@eel.upc.es Thesis Advisor: Xavier Aragones aragones@eel.upc.es Universitat Politècnica de Catalunya, Electronic Engineering Department High Performance Integrated Circuits Design Group Summary This work is concerned about the design process of high performance integrated circuits in presence of noise produced by large high-speed digital circuits in the same die. In a more specific context, it deals with the early estimation of the substrate and simultaneous switching noise produced by digital circuits, its propagation and, in minor extent, its impact in the noise sensitive radio frequency (RF) circuits integrated in the same die. The main goal is to produce efficient techniques to predict the noise in the early stages of an IC design process, that can be used to guarantee the correct operation of the circuits with regard to the substrate and switching noise produced by its digital part, whereas permit an earlier interaction between the different design teams involved in the design of System on Chip Circuits (SOCs) Provided that exhaustive circuit simulations using the typical models are impossible in realistic digital circuits, because of the complexity of the circuit as well as the complexity of the substrate models, it is necessary to propose simplified models that make possible simulation without significant loss of accuracy. On the other hand, in early stages of the design no detailed circuit description is available and the input signals in the circuit are undefined, then it is necessary to build probabilistic models of switching noise and find their relationships with the basic circuit characteristics in order to make possible early noise estimation. These issues imply research on basic questions such as which are the most significant mechanism of substrate injection in complex circuits; the relation of these mechanisms with the design decisions in high and low level design of digital circuits; the implications of substrate and power distribution parasitics on noise waveforms and on their propagation inside the digital section; the real importance of an accurate switching activity definition to predict noise versus accurate modeling of package-circuit parasitics that generate resonances; the stochastic models that can reproduce better the information of the digital circuit complexity; and the information needed to characterize properly these stochastic models, among others. As an outcome of research on these topics, methodologies for substrate and switching noise estimation at different phases of the design process of a SoC will be developed. At a very young stage of the design, noise activity is considered to be a random process whose parameters are related to very basic characteristics of the digital circuit by statistical techniques. In a more advanced stage of the design, noise activity is still modeled as a random process, but its parameters are already obtained from a structural definition of the circuit. Last, in a mature stage of the design, when both circuit structure and activity are defined, a deterministic macromodel of the generated noise is obtained. For this purpose, a methodology for substrate noise characterization and simulation of standard cells from a gate level description of the circuit will be created, making use of commercial tools available. All these methodologies will be evaluated in the design process of circuits that implement short-range wireless protocols and validated by comparing prediction results to experimental measurements on manufactured circuits. Contents OBJECTIVES 4 RESEARCH TOPIC FRAMEWORK 4 GENERAL OBJECTIVES 5 SPECIFIC OBJECTIVES 6 DETERMINISTIC MACROMODELS 6 STATE OF THE ART 7 SUBSTRATE MODELING 7 SUBSTRATE NOISE SOURCES. 8 SUBSTRATE NOISE MACROMODELING 9 SUBSTRATE NOISE STATISTICAL ESTIMATION 12 WORKPLAN 14 SCHEDULING 15 REFERENCES 17 APENDIX A PUBLICATIONS 20 Objectives Research topic framework Nowadays the CMOS technology permits the implementation of RF analog circuits, but only the less stringent applications may operate satisfactorily with the predominant CMOS technology on a single die, while the more technical demanding of these applications are likely for sometime to continue to require their implementation using different chips. The integration of High-speed digital circuits with RF analog circuits presents different challenges [Frye01], and one of the most important is related with the no perfect electrical isolation between the two different parts. The non- zero conductivity of the substrate permits interactions across the substrate between the circuits integrated in the same die, this interaction is called Substrate coupling. In order to clarify the substrate coupling problem suppose a system on chip circuit (SOC) like the one in figure 1. Fig1 Main Substrate Noise Sources The substrate is biased through a non-ideal package that permits voltage difference between the external reference and the substrate. Digital transients produce, by several mechanisms, changes in the substrate voltage that propagated to the analog and RF circuits can affect seriously their performance. A non-appropriate estimation for substrate noise leads to over-sized design and unpredictability of the system operation, a non-early estimation leads to time expensive redesign cycles and slower time-to-market. To pose a recent example, the design of a transceiver for wireless PAN [Zijl02] shows the importance of the estimation of substrate noise in the design of Wireless Systems-on-a-Chip: the measures taken in order to reduce the substrate noise impact in the RF front end (a huge P-type wall isolating the radio from the baseband with a costly low impedance connection to the external ground) could not be evaluated before the implementation with enough accuracy to guarantee the correct operation. Efficient evaluation of substrate noise injected by the large digital circuit could have permitted design iteration before the implementation process, and early estimation could speed up the design process and minimize costs. Several techniques have been proposed in the literature during the last years to predict substrate and simultaneous switching noise. Nevertheless, most these techniques are unfeasible in practice becasue they need SPICE simulations of the full circuits at transistor level, including parasitics. Some macromodeling techniques have also been proposed, but their validity is restricted to specific technologies (P+ substrates), a few noise injection mechanisms, or based on heuristic approaches. Last, some theory studies noise as a random process and discusses their spectral content, but no methodology has yet been developed to define that process from actual circuit characteristics. This work its part of a project called Pico-Self supported by the Spanish CICYT and EU FEDER funds under project TIC 2001-2337, which main objective its to develop design methodologies for self-powered mobile systems for personal area networks (PAN) integrated in CMOS technologies. Inside of this project we take charge of the methodologies for noise estimation and the design of the baseband circuit. General Objectives In this work we propose the use of circuital macromodels and statistical models of digital circuits in order to take into account the noise produced by the digital cells in an integrated environment. The main idea is to make possible the simulation or the estimation of the noise in order to avoid re- design and over-sized designs, and permit early interaction between the different teams involved in the design process (The Digital Baseband Team and the RF team) Fig 2. Because of the little information available in the first stages of the design, the noise estimation will be less accurate than that obtained in the last stages. These methodologies will be evaluated during the design of a system on a chip that implements a wireless protocol. The main objective can be summarized as: • To develop a methodology for digital circuit substrate noise simulation and estimation that allows obtain noise information in different stages during the design process of wireless systems on a chip. Fig 2. Digital Noise Information RF Team High Level Gate Low Level Layout - Wireless System on- Wireless System on chip. . chip Fig 2. Noise in the design process of a Wireless system on a Chip. Specific Objectives Two main topics can be differentiated in the proposed work: The first one is the development of techniques of simulation, using deterministic circuit macromodels of noise generation, than can be used in the two types of substrates most used (highly and lowly doped substrates) The second one is the study of non-deterministic models for the substrate noise and the relationship between their parameters with the digital circuital features. The objectives are detailed as: Deterministic Macromodels • To evaluate the importance of the main substrate injection mechanisms in large digital circuits: Noise due to power mesh bounce, capacitive coupling and switching interconnections. • To determine the influence of the physical implementation on noise magnitude and on the need of a detailed substrate model: substrate type, power mesh parasitics, package. • To determine the relevant device parasitics that should be included in a circuit noise macro- model: well capacitance, non-switching gates capacitance and others. • To efficiently include the influence of the electrical characteristics such as rise and fall times, clock frequency, fan-out, on the noise model of a digital gate. • To propose and verify a circuital noise model for standard cells. • To implement a procedure to generate a noise macro-model for a full circuit from noise models of individual cells. • To implement a procedure to evaluate the substrate noise from the HDL and floorplan description of the circuit. • To validate the proposed procedure by comparing results to measurements on a radio communication baseband processor implemented in a CMOS technology. Statistical estimation methods It is important to point that by means of stochastic models it is possible to deal with two different problems in the design process: the first one is the necessity of noise estimation when the complete digital design is not finished and the circuit has been not synthesized yet, the second one is the estimation when the circuit has been synthesized but there is no information about the inputs patterns, because they are not deterministic or because the rest of the circuits has been not finished. So the objectives are defined as: • To define a methodology for noise estimation in circuits previously synthesized in which the inputs are unknown or they are not deterministic. This includes determining which of the characteristics of cyclostationary noise are needed (mean width, mean magnitude, mean risetime, variance…), both in combinational and sequential circuits, and using statistical techniques to obtain those characteristics. • To define a methodology for noise estimation from global characteristics like: activity, gates number, operation frequency, datapath length, etc. by using statistical techniques to study how the resonant circuits inherent in the package-circuit parasitics are reflected in the noise power spectrum. State Of The Art The simulation of the noise produced by large Digital circuit has been object of numerous studies, and some different methodologies have been proposed. The most relevant of them are presented in four groups: In the section called Substrate Modeling the main methodologies for propagation modeling will be exposed. In the section substrate noise sources we grouped the works related with the study of the different sources of noise at the device level Next a revision of the most significant works in macromodeling of noise injected by large digital circuits will be treated in substrate noise macromodeling Finally we expose a revision of works in non-deterministic and statistical methodologies for noise prediction. Substrate Modeling There are several techniques for substrate modeling; each of them has an inherent trade-off accuracy/speed of extraction. The most accurate ones are very slow and take unacceptable time for both extracting and simulating large circuits. In the opposite corner the most efficient ones in terms of time of extraction have a low accuracy, which becomes unacceptable with increasing resolution and speed of signals. Five techniques are listed from most accurate to less accurate: • FEM, finite element methods, used in device simulators. They are based on the numerical solution of carrier continuity and Poisson equations [Su93, Arag95]. • FDM, finite difference methods. They numerically solve Ampere’s Law equation, neglecting magnetic field, which reduces the substrate to a RC mesh [Clem94,Stan94,Kana00]. Although it is a simplification of the previous technique, it also makes a full discretization of the substrate implying calculations with huge -though sparse- matrices, which slows down the extraction process. The accuracy obtained depends strongly on the discretization level. It deals with any technology, accepting horizontal and vertical variations of carrier concentration and material. • BEM, boundary elements method. It solves Laplace’s equation by finding the substrate’s Green function under determined contour conditions [Ghar96]. Only the discretization of ports is needed, and only port-to-port relations are modeled, leading to matrices sensibly smaller than in the FDM method. Nevertheless, matrices are dense, which makes computation times similar for small circuit extraction. But the main performance difference respect to FDM is accuracy: the substrate is treated as a few number of uniform layers. Thus, no horizontal variation is possible, and wells and trenches have to be treated as horizontal layers, as depicted in Fig. 3 [Clem01]. Both the FDM and the BEM techniques are techniques of choice in commercial tools because of their acceptable accuracy/efficiency trade-off. • Models using semi-empirical approximate formulas with technology and geometry dependence. • Single-node approximation. The whole substrate is considered as a single electrical node, which is reasonably valid approximation for P+ substrates, [Heij00, Su93]. Figure 3. Different modeling strategies for FDM and BEM techniques (extracted from [Clement01]). Because of the productivity requirements and complexity of the VLSI design including noise and signal integrity, new CAD tools covering this scope are appearing. We will mention here four known tools that have reached the commercial stage. • Space [Space] developed by the University of Delft, can use the BEM or interpolation formulas, depending on the accuracy wanted. • SCA [SCA] based on the boundary elements method. It was the first substrate parasitics extraction delivered by the top CAD vendor Cadence, although now it has been discontinued. • SeismIC [Seism], now distributed by Cadence. Uses the BEM as default, but may change to a FDM where more accuracy is needed • SubstrateStorm [SS02], now distributed by Cadence. Uses FDM, which provides high accuracy although slow extraction. Substrate Noise Sources. Identifying the potential substrate noise sources is the first step that has to be taken to perform an efficient prediction of substrate noise. A lot of work has been published to the date describing the mechanisms of substrate noise injection and trying to evaluate their importance. Fig. 4 depicts schematically the most relevant of these mechanisms, restricting to a digital domain. The obvious source of noise is the switching of the transistors in digital standard cells. A switching drain generates a disturbance current through the drain-substrate depletion capacitance. Also, impact- ionization currents contribute to the substrate disturbance. Several works have shown that drain- coupled disturbances are at least an order of magnitude larger than impact ionization for frequencies above 100 MHz [Char99] [Bria00]. Other transistor mechanisms such as DIBL or leakage currents have been shown to be negligible from the noise injection point of view. Another important source of substrate noise are the supply lines. Current peaks flowing through the package pin parasitics produce what is known as simultaneous switching noise (SSN) or dI/dt noise, which may result in large voltage peaks and ringing at the on-chip power supply lines. Given that in the standard cells the substrate and wells are biased by tying them to the power supplies, this SSN is not confined in the power nets, but injected to the substrate, therefore reaching other IC parts in different power-supply domains. Recently, a third potential source of substrate noise has been described, which is switching interconnects. It has been demonstrated that medium-sized, isolated interconnects may couple more substrate noise than hundreds of transistors. Nevertheless, in typical situations their contribution to substrate noise will not be that strong, since interconnects appear inside a complex routing mesh that creates shielding effects [Mart03]. In summary, we may distinguish three sources of substrate Fig. 4. Scheme of the potential sources of substrate noise. noise in the digital domain: transistors, interconnects, and SSN in power-supply lines Estimating the noise generated by complex digital cores may be a computationally expensive task, especially if all the potential noise sources are taken into account. If the estimation is to be fast and efficient, only the relevant noise injection mechanisms should be modeled, which leads to the question of whether a single dominant source may be identified as the substrate noise agent in all practical situations. Our previous experience and that of many authors, is that SSN introduced by substrate contacts is dominant over noise introduced by transistors and interconnects. For example, in [Arag99], the substrate noise injected by arrays of inverters in a 1.2 µm technology was analyzed and turned out to be originated by the digital supplies. Also in [Mart01] a complex circuit in a 0.35 µm technology was extracted and simulated, considering several package models. It was concluded that the substrate noise observed was always originated in the power-supplies, particularly by switching currents exciting package resonance. In [Heij02] the substrate noise generated by a 86Kgates ASIC is simulated for different packaging conditions, and even in the case where package was reduced to flip-chip bumps, the substrate noise was dominated by the power-supply noise. Similar conclusions are drawn from measurement results from [Briaire00], [Naga00], and [Timo91]. Substrate Noise Macromodeling The complexity of the electrical substrate and circuit models make impossible the simulation of circuits bigger than thousands of gates, simulations with hundreds of gates can take more than 80 hours for few clock cycles in a Sunblade 2000 workstation, an strict application of the current methodologies is clearly impossible for the actually >1Meg gates circuits. Simplified macromodels have been proposed in order to speed up the simulations, which the most relevant are [Mili96, Heij02]. In [Mili96] was proposed that the standard cells in a circuit behave like sources injecting current to the substrate. By means of Spice simulations of the each single standard cell Fig 5 were obtained the waveforms of these currents. Wc(t) Fig. 5 The standard cells like sources of current wc(t) that inject noise to the substrate. This process is made once per library and all the patterns are saved in a database in order to use them instead of the transistor models in a spice simulation. The total current injected by a complex circuit was calculated as: Sc i (t ) = ∑ ic (t ) c =1 This expression assumes that the substrate below the cells is a unique node (because otherwise the different currents shouldn’t be added), which is a good approximation for highly doped substrates (whose resistivity is between 1-50 mohms·cm). Sc is the set of standard cells in the circuit, and ic (t ) is the total current in the simulation time for the cell c. The current ic (t ) is calculated by means of a convolution between the switching activity, obtained from an event simulator, and the waveform wc(t), as: Wc(t) t end ic = ∑ trc (t − t ' ) wc (t ' ) Hdl Description t '= to Trc(t) Drive Even Driver Logic Simulator (like-Verilog) Input Vector Fig. 6 Procedure to calculate the current due to a standard cells using a event drive logic simulator The mainly drawbacks of this methodology are: • The methodology is only valid for high conductive substrates, while no discussion is included regarding its application to low conductive substrates, often used in SoC for wireless. According to the literature, noise attenuates with distance in those substrates, making the single-node approximation non valid. • The model doesn’t take into account the voltage drop in the package and in the internal power mesh. • The noise injected by the power mesh was not taken into account, and it has been shown to be the main source of noise [Arag99] [Mart01] [Naga99]. A posterior work [Heij02] takes in account the fluctuations in the power mesh introducing a circuit macromodel more detailed figure, Figure 7. Fig 7 Cell macromodel proposed in order to account the noise injected by the power mesh. This macromodel has three current sources instead of the one proposed by [Mili96]: the current injected by the vdd power line, the current injected by the vgnd power line and the current injected by the coupling capacitance. Also the circuit includes some parasitics: Rs, the substrate contact resistance to vss.; Rw, Cw such are the well contact resistance and the capacitance due to the well and the Cc that is “the circuit capacitances” and is not complete physically justified (there is not a standard procedure to calculate it). The next part of the procedure is similar to that exposed in [Mili96]. A big macromodel is build from the parallel arrangement of the individuals cells; three currents instead of only one form the database, the currents are convoluted like in Fig. 6 , and the total impedance are calculated as the result of the all cells contribution. Also in the big macromodel have been included models for the package and the I/O gates. This methodology was verified with a 64k circuit and achieved a 10% percent of error in that specific case. The drawbacks of this methodology are again, the single-node approximation only valid in high conductive substrates and, the parasitics that appear in the cell model that have no clear physical meaning, and the extraction of their values that is based on a semi-heuristic methodology. . Substrate Noise Statistical Estimation The two main sources of substrate noise are: the direct injection by switching transistors through the coupling capacitance, and the SNN In both cases these sources can be related with the gates activity and for complex digital circuits or circuits with non-deterministic inputs this activity can be seen like a random process. Regarding power bounce, current consumption estimation is the first step to obtain Substrate Noise estimation. In [Cipl96], [Frye01] the current consumption has been modeled has a cyclostationary random process reducing the problem of power estimation in the problem of obtain the mean and the covariance of the discomposed switching current. Current Tc Time Fig 8 Current consumption waveforms for a complex digital i i In order to clarify suppose that Fig. 8 shows a switching current signal. A typical method to find its spectrum is to consider the current waveform as the outcome of a random process [Frye01]. The analysis discomposes the switching current, as is showed in Fig. 8, into a sequence of pulses each of duration Tc The current can be expressed as: ∞ iD = ∑ i (t − nT n = −∞ n C ) (1) _____ The signal in (t ) can be represented as: in (t ) =µ (t ) + δ n (t ) when µ (t ) is in (t ) , and δ n (t ) is the different between both. It was demonstrated that the total spectrum is given by ∞ ∞ P( f )=F ∑ ( Rµ (τ − kTC ) + ∑ (C nm (τ − kTC ) (2) ∞ ∞ [Frye01], Where ∞ 1 Ru (τ ) = TC ∫ µ (t )µ (t − τ )dt −∞ And ∞ 1 C nm (τ ) = TC ∫δ −∞ n (t )δ n (t − τ )dt The discrete part of the spectrum arises from the periodic portion of the current waveform Ru (τ ) , in the other hand the continue part is due to the no periodic portion C nm (τ ) . This result is important because it has been pointed out that the part of the signal represented by the continuous spectrum is the most problematic, and also because the waveform of µ(t) have been related whit circuits parameters Fig9. µ(t) is remarkably similar for different circuits with similar rise and fall times, pulse width and dc average [Frye01]. Fig 9 Mean of the current consumption and some high level circuital parameters from [Frye02] In order to have a substrate noise estimation once the current spectrum is calculated is necessary to find the substrate noise spectrum, if the current process is a wide sense stationary process WSS, and the package model is as simple as an inductor, the spectrum of the internal ground voltage can be calculated as: S v (ω ) =Lω 2 S i (ω ) Although this works don’t propose a detailed methodology of design it shows the possibility of substrate noise estimation at high level. It is necessary to study the relationship between the continuous part of the spectrum with the circuit characteristics, the influence of the more complex resonances in the package model and the parameters necessaries to characterize the substrate noise like a random process. Workplan Work package 1 Bibliographical Review: Study of the substrate modeling and substrate simulation techniques for substrate noise generated by standard cells. Work Package 2 Deterministic Macromodel proposal: Comparison between the most important sources by means of simulation of representative circuits ISCAS. Development of a noise model for standard digital cells, accounting for the dominant sources of noise injection. Evaluation of the substrate short- circuiting effect of the power distribution network. Development of digital section noise macromodels from single cell macromodels. Methology for deterministic noise estimation from noise macromodels. Work Package 3 Laboratory measurements: Experimental verification of the deterministic macromodel in circuits previously fabricated.1) Test circuit containing sequential and combinational digital circuitry, together with noise sensors, developed in [Mart01] Master’s Thesis. 2) Bluetooth front-end, designed by Prof. Sanchez-Sinencio’s group, at the Texas A & M University. Work Package 4 Cyclestationary Process Validation: Validation of the cyclestationary assumption, definition of parameters necessaries to characterize the substrate noise like a cyclestationary random process Work Package 5 Statistical Simulation Evaluation: Simulation of circuits with statistical methods like Monte Carlo, parameters extraction in different circuits, evaluation of package resonance and its influence Work Package 6 Design of a Baseband Circuit for the Pico self project: Design and substrate noise estimation of a Baseband circuit for a wireless protocol in the Pico-Self project. Work Package 7: Dissemination of results Scheduling Jul’02- Jan’03 Jul’03- Jan’04 Jul’04- Jan’05 Jul’05- Jan’06 Dec’02 Jun’03 Dec’03 Jun’04 Dec’04 Jun’05 Dec’05 Jun’06 Bibliographical Review Laboratory measurements. Macromodel proposal. Cyclestationary Process Validation. Statistical Simulation Evaluation: Design of a Base band Circuit. Dissemination of results References [Arag95] X. Aragonès, F. Moll, M. Roca, A. Rubio, "Analysis and Modelling of Parasitic Substrate Coupling in CMOS Circuits", IEE Proceedings-Circuits Devices & Systems, vol. 142, no. 5, pp. 307-312, October 1995. [Arag99] X. Aragones, A. Rubio, “Experimental Comparison of Substrate Noise Coupling Using Different Wafer Types”, In IEEE Journal of Solid-State Circuits, Vol. 34, No.10, Octuber 1999. [Bada] M. Badaroglu, M. Heijningen, V. Gravot, S. Donnay, H. De Man, G. Gielen, M. Engels, I. Bolsens, “ High-Level Simulation of Substrate Noise Generation from Large Digital Circuits with Multiple Supplies”, In Proc. IEEE Design and Automation and Test In Europe, pp 326, 330, 2001. [Bran02] T. Brandtner, R. Weigel, “Hierarchical Simulation of Substrate Coupling in Mixed-Signal ICs Considering the Power Supply Network”, In Proc. Of the 2002 automation and test in Europe Conference and Exhibition”. [Bria00] Briaire, K. Krisch, “Principles of Substrate Crosstalk Generation in CMOS Circuits”, IEEE Trans. On Comp. Aided Design of Int. Circ. And Systems, vol. 9, no. 6, pp. 645-653, June 2000. [Bako90] H. B. Bakoglu, Circuits, Interconnections and Packaging for VLSI. Addison Wesley, Reading, MA, 1990. [Char99] E. Charbon, P. Miliozzi, L. Carloni, A. Ferrari, A. L. Sangiovanni-Vicentelli, “Modeling Digital Substrate Noise Injection in Mixed-Signal IC’s”, In IEEE Tran. On CAD, Vol. 18, No. 3, pp. 301-310, March 1999. [Clem94] F. Clement, E. Zysman, M. Kayal, M. Declercq, “LAYIN: Toward a Global Solution for Parasitic Couplign Modeling and Simulation”, Proc. IEEE 1994 Custom Integrated Circuits Conference, pp. 537-540, 1994. [Clem01] F. Clement, “Substrate Noise Coupling Analysis in Mixed-Signal ICs”, in IMEC 2001 Worskshop on Substrate Coupling [Cipl96] D.J. Ciplickas, R.A. Rohrer, “Expected Current Distributions for CMOS circuits” in Digest of technical papers IEEE/ACM International Conference on Computer-Aided Design, pages 582-592, nov. 1996. [Deme99] A. Demir, J. Roychowdhury, “Modeling and Simulation of Noise in Analog/Mixed- Signal Comunications Systems”, In Proc. IEEE CICC, pp 385-392, 1999 [Frye01] R. C. Frye, “Integration and Electrical Isolation in CMOS Mixed-Signal Wireless Chips”, in Proceedings of the IEEE, Vol. 89, No. 4, pages 444-455, April 2002. [Frye00] R. C. Frye, “Switching-Induced Noise and Mixed-Signal Receiver Design”, In Southwest symposium on Mixed-Signal Design, pages 119-134, 2000. [Ghar96] R. Gharpurey, R.G. Meyer, "Modeling and Analysis of Substrate Coupling in Integrated Circuits", IEEE J. Solid-State Circuits, vol. 31, no. 3, pp. 344-353, March 1996. [Heij02] M. Heijningen, M. Badaroglu, S. Donnay, G. Gielen, H. J. De Man, “Substrate Noise Generation in Complex Digital Systems: Efficient Modeling and simulation Methodology and Experimental Verification”, In IEEE Journal on Solid-State Circuits, Vol. 37, No. 8, August 2002. [Heij00] M. Heijningen, M. Badaroglu, S. Donnay, M. Engels, I. Bolsens, “High-Level Simulation of Substrate Noise Generation Including Power Supply Noise Coupling”, In Proc. Design Automation Conference, pp446 –451, 2000. [Kana00] J. Kanapka, J. Philips, J. White, “Fast Methods for Extraction and Sparsification of Substrate Coupling”, IEEE Design Automation conference, DAC’00, pp. 738-743, 2000. [Mart01] Martorell, Ferran “Aportació a la modelació i anàlisi de l’acoblament a través del substrat en circuits integrats CMOS,” PFC thesis, Universitat Politècnica de Catalunya, 2001.[Mart03] F.Martorell, D. Mateo, X. Aragones, “Modeling and Evaluation of Substrate Noise Induced by Interconnects,” Proceedings of DATE'03, pp. 524-529. Munich, March 2003. [Mitra95] S:Mitra, R. A. Rutenbar, L.R. Carley, D.J. Allstot, “Substrate-aware mixed-signal macrocell placement in WRIGHT”, In IEEE Journal of Solid-State Circuits , Vol. 30, Issue: 3 , Page(s): 269 –278, March 1995. [Mili96] P. Miliozzi, L. Carloni, E. Charbon and A. L. Sangiovanni-Vicentelli, “SUBWAVE a Methodology for Modeling Digital Substrate Noise Injection in Mixed-Signal Ics”, in Proc. IEEE CICC, pp. 385-388, May 1996. [Naga99] M. Nagata, Y. Kashima, D. Tamura, T. Morie, A. Iwata, “Measurements and Analyses of Substrate Noise Waveform in Mixed Signal IC Enviroment” In Proc. IEEE Custom Integrated Circuits Conference, pp 575-578, 1999. [Naga00] M. Nagata, J. Nagai, T. Morie, A. Iwata. “ Measurements and Analyses of Substrate Noise Waveform in Mixed Signal IC Enviroment” In IEEE Transaction on Computer-Aided Design of Integrated Circuits and systems, vol.19, No.6, pp 671-678,2000. [Najm91] F.N. Najm, R. Burch, P. Yang, “ Probabilistic Simulation for Reliability Analysis of CMOS VLSI circuits” in IEEE trans. On Computer-Aided Design, Vol. 9, No 4, November 1990. [Naga01] M. Nagata, J. Nagai, K. Hijikata, T. Morie, A. Iwata. “Physical Design Guides for Substrate Noise Reduction in CMOS Digital Circuits”, In IEEE Journal on Solid-State Circuits, Vol. 36, No. 36, pp 539-549, 2001. [Osor03] J.F. Osorio, L. Elvira, F. Martorell, J.L. Gonzalez, X. Aragones, “Substrate Noise Macro- Modeling of Digital Cores”, submitted to XVIII Conference on Design of Circuits and Integrated Systems 2003. [Seism] http://www.cadence.com/datasheets/cadMOSSeism.html [SCA] http://www.cadence.com/datasheets/dat_pdf/sca446apn.pdf [Stan94] B.R. Stanisic, N.K. Verghese, R.A. Rutenbar, L.R. Carley, D.J. Allstot, "Addressing Substrate Coupling in Mixed-Mode IC's: Simulation and Power Distribution Synthesis", IEEE J. Solid-State Circuits, vol. 29, no. 3, pp. 226-237, March 1994. [Space] http://cas.et.tudelft.nl/~space/ [SS02] SubstrateStormCDS Release 3.5. Cadence Design Systems. June 2002 [Sve99] L.J. Svensson, S. Mattisson, “Harmonic Content of Digital CMOS switching waveforms”, in Southwest Symposium on Mixed-Signal Design, pp 128-133, 1999. [Su93] D.K. Su, M.J. Loinaz, S. Masui, B.A. Wooley, "Experimental Results and Modeling Techniques for Substrate Noise in Mixed-Signal Integrated Circuits", IEEE J. Solid-State Circuits, vol. 28, no.4, pp. 420-430, April 1993. [Timo91] Timothy J. Schmerbeck, R. Richetta, Larry Smith, “A 27MHz Mixed Analog/Digital Magnetic Recording Channel DSP Using Partial Response Signaling with Maximum Likelihood Detection”, IEEE International Solid-State Circuits Conference, pp. 136-137, 1991. . [Zijl02] P.V. Zeijl, J. T. Eikenbroek, P. Vervoort, S. Setty, J. Tangenberg, G. Shipton, E. Kooistra, I. Keekstra, D. Belot, K. Visser, E. Bosma, S. Blaakmer, “A Bluetooth Radio in 0.18-um Cmos”, In IEEE journal of Solid-State Circuits, Vol. 37, No. 12, page(s) 1679-1687 December 2002 [Verg95] N. K. Verghese, T. J. Schmerbeck, and D. J. Allstot, Simulation techniques and solutions for Mixed-Signal Coupling in Integraded Circuits”, Norwood, MA: Kluwer, 1995. APENDIX A Publications

DOCUMENT INFO

Shared By:

Categories:

Tags:
substrate noise, substrate coupling, noise generation, modeling and simulation, power dissipation, analog circuits, power consumption, signal integrity, the noise, power supply, filter paper, high-level synthesis, insoluble solids, product inhibition, enzymatic hydrolysis

Stats:

views: | 8 |

posted: | 4/18/2010 |

language: | |

pages: | 20 |

OTHER DOCS BY zed42768

How are you planning on using Docstoc?
BUSINESS
PERSONAL

By registering with docstoc.com you agree to our
privacy policy and
terms of service, and to receive content and offer notifications.

Docstoc is the premier online destination to start and grow small businesses. It hosts the best quality and widest selection of professional documents (over 20 million) and resources including expert videos, articles and productivity tools to make every small business better.

Search or Browse for any specific document or resource you need for your business. Or explore our curated resources for Starting a Business, Growing a Business or for Professional Development.

Feel free to Contact Us with any questions you might have.