ECE 524 Synthesis and Verification of Digital Circuits
Binary decision diagrams, finite state machines and finite automata. Design
automation concepts in logic level synthesis, optimization and verification for
combinational as well as sequential logic. Technology mapping.
Course Total Credit Hours: 3 Lecture: 3 Laboratory: - Project -
Prerequisites: ECE 423, ECE 425 or consent of instructor
Course Coordinator: Spyros Tragoudas
1. “Logic Synthesis and Verification algorithms”, G.D. Hachtel and F. Somenzi, Kluwer
Academic Publishers, Second printing, 1998.
1. “Synthesis and Optimization of Digital Circuits”, G. De Michelli, Mc-Graw Hill, 1994.
2. Papers from journals and conference proceedings.
1. To provide graduate students with the ability to design or improve
automation tools for architectural and logic level synthesis.
2. To provide graduate students with the ability to design or improve
automation tools for logic and timing verification.
1. Design the data path of digital system benchmarks.
2. Timing verification of digital circuit benchmarks.
3. Automated synthesis of digital circuit benchmarks.
Major CAD Packages
Last Review: Fall Semester 2005 Signature: