# Lecture 15 - Digital Circuits Inverter Basics

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```					                            6.012 - Electronic Devices and Circuits
Lecture 15 - Digital Circuits: Inverter Basics - Outline
• Announcements
Handout - Lecture Outline and Summary
The MOSFET alpha factor - use definition in lecture, not text
["+1" is missing in Eq. 10.23]
• Review - Linear equivalent circuits
Notation: iD = ID + id(t) where iD = total current; ID = bias; id(t) = increment
LECs: the same for npn and pnp; the same for n-MOS and p-MOS;
all parameters depend on bias, so maintaining a stable bias is critical
• Digital building blocks - inverters
A generic inverter
MOS inverter options
• Digital inverter performance metrics
Transfer characteristic: logic levels and noise margins
Power dissipation
Switching speed
Fan-out, fan-in
Manufacturability
• Comparing the MOS options
And the winner is….
Clif Fonstad, 10/03                                                        Lecture 15 - Slide 1
• LEC for the p-n junction diode:

A                                   a

qAB
IS                                       gd          Cd

B                                   b
q                   q ID
gd =        IBS e qVAB / kT ª
kT                    kT
qeSi N Ap
Cd = Cdp + Cdf , where Cdp (VAB ) = A                      and
2 (f b - VAB )
†                        2                                    2
q I [w p - x p ]                         [w p - x p ]
Cdf (VAB ) = D                 = gd t d with t d ≡
kT      2De                                  2De

(Note: The capacitance expressions assume an n+-p diode)
Clif Fonstad, 10/03                                                              Lecture 15 - Slide 2
†
• Linear equivalent circuit for the BJT in F.A.R:
qBC                C                                            Cm
b                                                         c
iB’            bFiB’                     +
gp    vp                    gmv p         go
B                                                              Cp
IBS                                -
e                                                         e
qBE                E

q IC                         gm
gm ª                         gp =
kT                          bo
Ê     IC ˆ
go ª l IC       Áor ª    ˜
Ë     VA ¯
2
wB
C p = gm t b + B - E depletion capacitance, where t b =
2 Dminority
.in base
Cm = B - C depletion capacitance

Clif Fonstad, 10/03          (Note: The LEC is the same for npn and pnp BJTs.        Lecture 15 - Slide 3
†
• Linear equivalent circuit for the MOSFET in saturation:
Cgd
D                        g                                                       d
qDB              +                                                   +
qG                              v gs                                                v
Cgs             gmv gs     gmb v bs     go ds
iD                    -                                                   -
G                           B        s-                                                      s
v bs                                    Cdb
S         qSB                      Csb     Cgb
b+
gm ª     2K ID
Ê     ID ˆ
go ª l I D         Áor ª    ˜
Ë     VA ¯
1      eSiqN A
gmb = h gm = h 2K ID                with    h=     *
Cox    qf p - VBS
2      *
Cgs =     W L Cox      Csb , Cgb , Cdb : depletion region capacitances
3
*          *
Cgd   = W Cgd where Cgd is the gate - to - drain fringing and overlap
capacitance per unit gate width
Clif Fonstad, 10/03 (Note: The LEC is the same for n- and p-channel MOSFETs. Lecture 15 - Slide 4
Circuit symbols:                         C                           E

BJT:         B                             B

E                           C
npn                        pnp (usual circuit
MOSFET:                                                    orientation)

D                   D                        S                       S

G                     B G               B        G                B G                     B

S                  S                         D                      D
Enhancement mode        Depletion mode         Enhancement mode        Depletion mode

n-channel                      p-channel (usual circuit orientation)
Clif Fonstad, 10/03                                                      Lecture 15 - Slide 5
• Building Blocks for Digital Circuits: inverters
V DD
A basic                                                               Performance metrics
v IN       vOUT           •      Transfer characteristic
inverter                  Pull-                                       •      Logic levels
Up             Lo (0) Hi (1)
•      Noise margins
Switch:                                   Hi (1) Lo (0)               •      Power dissipation
on or off                              +
+                     vOUT
•      Switching speed
vIN
–                     –                               •      Fan-in/Fan-out
•      Manufacturability
†
Logic gates                                                          V DD
Memory cell
V DD                                                                    V DD
NOR:                                                           Pull-
NAND:              Up
vA    vB   vOUT      Pull-                                                                Pull-          Pull-
Up                    vA   vB       vOUT                             Up             Up
0     0    1                                                                 +
0     1    0                                0   0         1 +
+
1     0    0    +    +                      0   1         1 vA              vOUT
vOUT
vA   vB                      1   0         1
1     1    0    –    –           –                             +
vB
1   1         0   – –            –
Flip-flop
Clif Fonstad, 10/03                                                                                 Lecture 15 - Slide 6
†
†
V DD
V OUT    Logic levels,
Transfer characteristic                                                             Noise margins
Node equation : iPD = iPU                                                 V HI
Pull-
Ï      0                                      Up
Ô                                                   iPU
Ô           when v IN < VT ,PD
ÔK PD (v IN - VT ,PD ) 2 2
iPD = Ì                                                iPD +              VM
Ô when 0 < [v IN - VT ,PD ] < vOUT    +              vOUT
ÔK PD (v IN - VT ,PD - vOUT 2)vOUT   vIN
Ô                                      –              –             V LO
Ó   when 0 < vOUT < [v IN - VT ,PD ]
V IN
iPU : Depends on the specific pull - up device used.                             V LO V 1L V M V 1H     V HI
V DD                                V DD                    NML           NMH

Switching
†
Pull-                                                          Power
iPU                    Pull-
times                Up                              Up i
PU                     PTotal = PStatic + PDynamic
iDischarge     Static :
Static:
+
OFF LO         CL          ON            +                                   1
+                                                 HI           CL           PStatic =      iPU ,onVDD
HI to LO           to                 +                to                                   2
HI              LO to HI
–                  –                              LO                   Dynamic :
–        iPD      –                    Dynamic:
2
PDynamic = CLVDD ⋅ f
Charging cycle: iCharge = iPU               Discharging cycle:
Clif Fonstad, 10/03                               iDischarge = iPD – iPU                     Lecture 15 - Slide 7

†
V DD                                             V DD
MOS
inverters                      Pull-                                                     RL
Up                                    Resistor
pull-up
Generic                                                                                 +
+
inverter                                            CL
+                 v OUT                              +               v OUT
v IN                                                 v IN
–                  –                                 –                   –

V DD                                V DD                        V DD                               V DD

V GG
(>>V DD )

+                                  +                           +            +                     +
+                  v OUT       +                  v OUT         +                v OUT        v IN                v OUT
v IN                           v IN                             v IN
–                  –           –                      –         –                 –               –                  –

n-channel, e-mode pull-up                                   n-channel,                p-channel, e-mode
VDD    on gate            VGG on gate                             d-mode pull-up                pull-up (CMOS)
Clif Fonstad, 10/03                                                                                      Lecture 15 - Slide 8
V DD                                        V DD

Switching                      Pull-    iPU                            Pull-
Up                                      Up i
transients                                    iCharge                        PU
iDischarge
+                         ON            +
OFF LO           CL                             HI          CL
+          to                         +                to
HI to LO        HI                      LO to HI            LO
–               –                     –        iPD      –

Charging cycle: iCharge = iPU        Discharging cycle: iDischarge = iPD – iPU
iCharge

The charging
currents with                       CMOS, I ON = 0
various pull-ups
n-ch, d-mode
ION
resistor and n-ch, e-mode
w. V GG on gate
n-ch, e-mode
V DD on gate
vOUT
Clif Fonstad, 10/03                                                          V DD       Lecture 15 - Slide 9
i Discharge
Switching transients                     + iPU

The discharging currents
with various pull-ups
Note: The discharge current is the                  n-ch, d-mode
difference between the upper curve         ION
and the appropriate lower curve.                       resistor and n-ch, e-mode
w. V GG on gate
n-ch, e-mode
V DD on gate
V DD                                                           vOUT
V DD
i Discharge
Pull-                (iPU = 0)
Up i                               CMOS
PU
iDischarge
ON           +
HI          CL
+                to
LO to HI             LO
–        iPD     –
vOUT
Clif Fonstad, 10/03                                   Lecture 15 - Slide 10   V DD
Switching transients:                                                      summary of charge/discharge currents
V DD                                  V DD
iCharge                   iDischarge
Resistor and E-                 RL                V GG
mode pull-up                                (>>V DD )

+                                   +
(VGG on gate)          +            v OUT          +                   v OUT
v IN                        v IN                                        v OUT                             v OUT
–              –            –                      –

V DD
V DD                              V DD
iCharge                  iDischarge
E-mode pull-up
(VDD on gate)                                        +
+                   v OUT
v IN
–                       –
v OUT                             v OUT
V DD                            V DD                              V DD
iCharge                  iDischarge
D-mode pull-up
(called "n-MOS")                                                +
+                   v OUT
v IN
–                       –                          v OUT                             v OUT
V DD
V DD                              V DD
iCharge                   iDischarge

CMOS
+                     +
v IN                 v OUT
–                     –
v OUT                             v OUT
Clif Fonstad, 10/03                                                                         V DD                              V DD
Lecture 15 - Slide 11
6.012 - Electronic Devices and Circuits
Lecture 15 - Digital Circuits: Inverter Basics - Summary
• Digital building blocks - inverters
A generic inverter - Switch = pull-down device, Load = pull-up device
MOS inverter options - Pull-down: n-channel, e-mode (faster than p-channel)
Pull-up: 1. resistor; 2. n-channel, e-mode w. and w.o. gate bias;
3. n-channel, d-mode; 4. p-channel, e-mode (CMOS)
• Digtial inverter performance metrics
Transfer characteristic
Logic levels: VHI, VLO
Noise margins: NMHI (high), and NMLO (low)
Design variables: choice of pull-up device
pull-up and pull-down thresholds
device sizes (absolute and relative)
Power dissipation: stand-by power and switching dissipation
charge and discharge currents critical
Fan-out, fan-in: minimal issue in MOS; more so with BJT logic
Manufacturability: small, fast, low-power, reliable, and cheap
• Comparing the MOS options
And the winner is….CMOS
Clif Fonstad, 10/03                                                       Lecture 15 - Slide 12

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