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Sequential Systems Review Sequential System Diagram
n m
• Combinational Network
Combinational
– Output value only depends on input value Logic
Circuit
• Sequential Network
k-bit k-bit
– Output Value depends on input value and present state Present State Next State
value Value Memory Elements Value
- flip-flop
– Sequential network must have some way of retaining - latch
k - register k
state via memory devices. - PROM
– Use a clock signal in a synchronous sequential system
to control changes between states • m outputs only depend on k PS bits - Moore Machine
– REMEMBER: Moore is Less !!
• m outputs depend on k PS bits AND n inputs - Mealy Machine
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Slide by Prof Mitch Thorton
Clock Signal Review
Memory Elements
Memory elements used in sequential systems are flip-flops
Pw and latches.
rising edge falling edge
D Q(t+1) Q(t+1) is Q next
voltage
0 0 state
τ - period (in seconds) Pw - pulse width (in seconds) D
Q 1 1
time f - frequency pulse width (in Hertz) f = 1/τ
C D flip flop (DFF)
duty cycle = Pw /τ Flip-flops are edge triggered
duty cycle - ratio of pulse width to period (in %)
(either rising or falling edge).
millisecond (ms) Kilohertz (KHz)
10
-3
10
3 D
microsecond (µs) Megahertz (MHz) Q Latches are level sensitive. Q
-6 6
10 10
G D latch (DL) follows D when G=1, latches
nanosecond (ns) Gigahertz (GHz)
10
-9
10
9 when G goes from 1 to 0.
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Slide by Prof Mitch Thorton
D FF, D Latch operation
Other State Elements
J J K Q(t+1) JK useful for single bit
Q 0 0 Q(t)
flags with separate
0 1 0 set(J), reset(K) control.
C for FF, G for latch C 1 0 1
K 1 1 Q’(t)
D input
T T Q(t+1) Useful for counter
Q 0 Q(t) design.
Q (FF)
C 1 Q’(t)
Q (DL)
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DFFs are most common Synchronous vs Asynchronous Inputs
• Most FPGA families only have DFFs Synchronous input: Output will change after active clock edge
Asychronous input: Output changes independent of clock
• DFF is fastest, simplest (fewest transistors) of
FFs State elements often have async set, reset control.
S
• Other FF types (T, JK) can be built from DFFs D input is synchronous with respect to Clk
D
• We will use DFFs almost exclusively in this Q
class C S, R are asynchronous. Q output affected by S, R
– Will always used edge-triggered state elements (FFs), not R independent of C. Async inputs are dominant over
level sensitive elements (latches). Clk.
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D FF with async control
FF Timing
• Propagation Delay
C – C2Q: Q will change some propagation delay after
change in C. Value of Q is based on D input for DFF.
– S2Q, R2Q: Q will change some propagation delay after
D input change on S input, R input
– Note that there is NO propagation delay D2Q for DFF!
Q (FF) – D is a Synchronous INPUT, no prop delay value for
synchronous inputs
R
S
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Setup, Hold Time
Setup, Hold Times
tsu thd
• Synchronous inputs (e.g. D) have Setup, Hold
time specification with respect to the CLOCK
C
input
• Setup Time: the amount of time the synchronous
input (D) must be stable before the active edge of Stable
clock D changing D changing
• Hold Time: the amount of time the synchronous
input (D) must be stable after the active edge of If changes on D input violate either setup or hold
clock. time, then correct FF operation is not guaranteed.
Setup/Hold measured around active clock edge.
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Registers 1 Bit Register using DFF, Mux
The most common sequential building block is the register. A
register is N bits wide, and has a load line for loading in a new
value into the register.
0 2/1 Mux DFF
Register contents do not change
DIN unless LD = 1 on active edge of DIN Y D
1 DOUT
clock. Q
N R DOUT S
CLK LD C
E
LD G N A DFF is NOT a register! DFF R
contents change every clock CLK
ACLR edge. ACLR
ACLR used to asynchronously Note that DFF simply loads old value when LD = 0. DFF
clear the register is loaded every clock cycle.
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1 Bit Register using Gated Clock Counter
DIN DFF
DOUT Very useful sequential building block. Used to generate memory
LD Ld* Ldclk D Q addresses, or keep track of the number of times a datapath
CLK C operation is performed.
R
ACLR DFF DIN LD asserted loads
C counter with DIN value.
Clk D N
Q CLK N CNT_EN asserted will
LD T
C N increment counter on
LD R
Ld* next active clock edge.
EN
Ldclk CNT_EN
ACLR will
Saves power over previous design since DFF is not clocked every clock ACLR asynchronously clear
cycle. Many FPGAs offer an ‘enabled’ DFF as an integrated unit. Gating the counter.
can be optimized at transistor level in ‘enabled’ DFF.
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One way to build a Counter Incrementer: Combinational Building
CNT_EN Block
Incrementer EN EN
Y When EN=1, Y = DIN + 1
DIN Y
DIN N When EN=0, Y = DIN
N
0 DFF
DIN N Y DIN DIN2 DIN1 DIN0
1
N EN
LD N S
N Etc...
CLK
R
ACLR
Y2 Y1 Y0
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Counter Operation Counter Timing (8 Bit register)
CLK
Counter A
Aclr Clk En LD Q Q+ Op
Din $ 85 $ A0 $ EF $ 83
H X X X X 0 Async Clr
L ↑ X H X Din Load LD Inc Hold
L ↑ H L Q Q+1 Increment
Cntr Load
L X L L Q Q Hold EN
Dout $ 00 $ A0 $ A1 $ A2
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Another Counter (Cntr ‘B’)
DIN
N Counter Operation
LD S
Counter B
1
Y Aclr Clk En LD Q Q+ Op
0
H X X X X 0 Async Clr
Incrementer
L ↑ L H X Din Load
DFF
DIN
L ↑ H L Q Q+1 Increment
EN N Y D L X L L Q Q Hold
EN N
L ↑ H H Q Din+1 Load Inc
Q
CLK N
R
ACLR EN=H, LD=H will load an incremented version of Din
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Cntr ‘A’ with SCLR Input
Synchronous vs Asynchronous Clear EN
• The ACLR line is tied to the asynchronous reset of Incrementer EN
the DFF Y
DIN
– Asynchronous clear is independent of clock, will occur
anytime clear is asserted 0 DFF
– Usually tied to Power-On-Reset (POR) circuit Y
DIN N 1
– Not very useful for normal operation since any glitch N D
N
on ACLR will clear the counter LD N S Q
• Would like a Synchronous Clear input (SCLR) in SCLR N
which the clear operation takes place on the next CLK R
active clock edge.
ACLR
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Parallel Data Transfer
Counter Operation To transfer data between two computers, we can do it in
parallel:
Clk
Counter A with SCLR C C
P DX[7:0] P
Aclr Sclr Clk En LD Q Q+ Op U U
#1 8 #2
H X X X X X 0 Async Clr
L H ↑ X X X 0 Sync Clr CLK
L L ↑ X H X Din Load
L L ↑ H L Q Q+1 Increment
L L X L L Q Q Hold DX $ 85 $ A0 $ EF $ 83 $ 75 $ 13
Parallel Data transfer requires a lot of lines to be run between
computers; cabling be expensive, and bulky. Not practical for
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long distances. BR 8/99 26
Serial Data Transfer More on Serial Data Transfer?
We can transfer data in serial fashion, e.g., one bit at a time.
• Serial data transfer is more common than data
Clk
C C parallel communication because less wires than
P DX P parallel data transfer, can be run longer distances
U U • Data can be transferred either LSB (least
#1 #2
significant bit) to MSB (most significant bit) or
CLK vice-versa
– Most common is LSB to MSB
DX • To implement serial data transfer we need a
sequential building block that is called a SHIFT
1 0 1 0 0 0 0 1 register.
bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7
$ 85 = 10000101, data transmitted LSB to MSB
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Shift Register Shift Register Timing (SI = 0)
Very useful sequential building block. Used to perform either CLK
parallel to serial data conversion or serial to parallel data
conversion.
Din $ 85
LD asserted loads register with
DIN DIN value. LD
N S DOUT EN asserted will shift data on
CLK H next active clock edge. EN
I
LD N ACLR is async clear.
F
T DOUT $ 00 $ 85 $ 42 $ 21 $ 10 $ 08 $ 04 $ 02
EN SI is serial data in.
E
ACLR R Look at LSB of DOUT for serial
data out. DOUT0
SI (LSB)
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Understanding the shift operation Right Shift vs Left Shift
A right shift is MSB to LSB
MSB LSB
$85 = 1 0 0 0 0 1 0 1 In: D7 D6 D5 D4 D3 D2 D1 D0
SI = 0 SIN
$42 = 0 1 0 0 0 0 1 0 1st right shift Out: SIN D7 D6 D5 D4 D3 D2 D1
SI = 0
2nd right shift A left shift is LSB to MSB
$21 = 0 0 1 0 0 0 0 1
SI = 0 In: D7 D6 D5 D4 D3 D2 D1 D0
SI
$10 = 0 0 0 1 0 0 0 0 3rd right shift
Out: D6 D5 D4 D3 D2 D1 D0 SI
Etc….
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D0 I0 Y
Combinational Right Shifter D1 I1 Y0 4-bit Combinational
S RIGHT Shifter
EN Implementation
We need a combinational block that can either shift right or I0 When EN = 0, then:
D1 Y
pass data unchanged I1 Y1
D2 Y = D3 D2 D1 D0
SRIGHT S
When EN = 1, Y = D
D Y shifted right by 1 position.
N
N D2 I0 Y When EN = 1, then:
SI When EN=0, Y = D Y2
I1
EN D3 Y = SI D3 D2 D1
S
(right shifted by one
D3 I0 Y position)
I1 Y3
SI
S
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D0 I0
I1
Y Y0 4-bit Combinational Shift Register (Right shift) Implementation
SI SI
S LEFT Shifter
Implementation EN
EN EN
D1 I0 Y When EN = 0, then:
Y1 Right Shifter SI
D0 I1 Y
Y = D3 D2 D1 D0 D
S
0 DFF
D2 I0 Y When EN = 1, then:
I1 Y2 N Y
D1 DIN 1 D
S Y = D2 D1 D0 SI N
LD N S Q
(left shifted by one
CLK N
D3 I0 Y position) R
I1 Y3
D2 ACLR
S
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Serial Communication Shift Register Timing (SI_A = 0)
CLK
CPU A CPU B
DA $ 85
DA[7..0] DB[7..0]
1 2 3 4 5 6 7 8
S QA[7..0] 8 S QB[7..0]
8 LDA
H CLK H
CLK
I I EN
LDA 8 LDB 8 QA
F F
EN T $ 00 $ 85 $ 42 $ 21 $ 10 $ 08 $ 04 $ 02 $ 01 $ 00
EN T
E E
ACLR ACLR R QA0
R
SI_A QA0 SI_B QB
$ 00 $ 80 $ 40 $ A0 $ 50 $ 28 $ 14 $0A $ 85
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Comments on Shift operation Sequential System Description
• Took 8 clock cycles to serially send the 8 bits in CPU A to • The Q outputs of the flip-flops form a state vector
CPU B.
• A particular set of outputs is the Present State (PS)
• Shift Register at CPU A ended up at $00; Shift Register at
CPU B ended up with CPU A value ($85) • The state vector that occurs at the next discrete
• Initial contents of CPU B shift register does not matter time (clock edge for synchronous designs) is the
• Data shifted out LSB to MSB from CPUA to CPUB. Note Next State (NS)
that data enters the MSB at CPUB and progresses toward • A sequential circuit described in terms of state is a
the LSB. Finite State Machine (FSM)
– Not all sequential circuits are described this way; i.e.,
registers are not described as FSMs yet a register is a
sequential circuit.
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Describing FSMs Example State Machine
0
• State Tables S0
1
S0
• State Equations CNT 0
1 0
• State Diagrams 1
S2
• Algorithmic State Machine (ASM) Charts S1
0
– Preferred method in this class S1 1
CNT 0
• HDL descriptions
1
State Diagram
(Bubble Diagram) S2
CNT 0
ASM Chart
1
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State Assignment FSM Implementation
State assignment is the binary coding used to represent the states
Use DFFs, State assignment: S0 = 00, S1 = 01, S2 = 10
Given N states, need at least log2(N) FFs to encode the states
(i.e. 3 states, need at least 2 FFs for state information). PS NS
State Table
Inc Q1 Q0 Q1+ Q0 D1 D0
S0 = 00, S1 = 01, S2 = 10 (FSM is now a modulo 3 counter) 0 0 0 0 0 0 0
0 0 1 0 1 0 1 Equations
0 1 0 1 0 1 0
0 1 1 x x x x D1 = Inc’Q1Q0’ + IncQ1’Q0
Do not always have to use the fewest possible number of FFs.
A common encoding is One-Hot encoding - use one FF per state. 1 0 0 0 1 0 1
1 0 1 1 0 1 0 D0 = Inc’Q1’Q0 + IncQ1’Q0’
S0 = 001, S1 = 010, S2 = 100 1 1 0 0 0 0 0
1 1 1 x x x x
State assignment affects speed, gate count of FSM
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FSM Usage
Minimize Equations (if desired)
• Custom counters
D1 • Datapath control
Q1Q0
Inc 00 01 11 10
D1 = Inc’ Q1 + Inc Q0 R
0 0 0 x 1 E
1 0 1 0 DIN G R DOUT
x E X
+
D0 R G
Q1Q0 E
Inc 00 01 11 10 G
0 0 1 x 0 D1 = Inc’ Q0 + Inc Q1’Q0’
1 1 0 x 0 FSM Control (reg load lines, mux selects)
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Summary
• We will be describing sequential systems via
VHDL and ASM charts
– Use ASM chart for human reader, VHDL to allow
synthesis of the design
– Synthesis will perform combinational minimization,
but not state reduction.
• Will use common sequential building blocks
extensively
– Registers, Counters, Shift registers, Memories
• Basic storage element will be DFF
• Synchronous (edge-triggered) design methodology
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