Memory Management Motivation Background Logical (Virtual) vs

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Memory Management Motivation Background Logical (Virtual) vs Powered By Docstoc
					        Memory Management                                               Motivation
•   Motivation                                    • Much of this chapter archaic
•   Background                                    • Next chapter (virtual memory) more real
                                                     – basis for understanding need for VM
•   Swapping
                                                  • Old ideas come back
•   Contiguous Allocation
                                                     – embedded systems
•   Paging                                           – PDAs
•   Segmentation                                     – FPGAs
•   Segmentation with Paging
                                                     small simple memory systems still exist
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                                                   Binding of Instructions and Data to
            Background                                           Memory
                                                   binding of instruction, data addresses to memory addresses
• Program must be brought into memory              possible times
  and placed in process for it to be run              • Compile time: if memory location known a
                                                        priori, absolute code can be generated; must
                                                        recompile if starting location changes
• Input queue – collection of processes on            • Load time: must generate relocatable code if
  disk waiting to be brought into memory to             memory location unknown at compile time
  run programs                                        • Execution time: binding delayed until run time
                                                        if process can be moved during execution;
                                                        need hardware support to map addresses
• User programs go through several steps                (e.g., base + limit registers)
  before being run
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          Multistep Processing                             Logical (Virtual) vs.
           of a User Program                             Physical Address Space
                                                  • Concept of logical address space bound to separate
                                                    physical address space central to memory management
                                                     – logical address – generated by CPU (later: virtual address)
                                                     – physical address – address seen by memory unit at low level
                                                  • Logical and physical addresses same in compile-time
                                                    and load-time address-binding; logical and physical
                                                    addresses differ in execution-time address-binding

                                                  slight over-simplification – VM (next chapter) another layer

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   Memory-Management Unit                                Dynamic relocation using a
           (MMU)                                            relocation register
• Hardware maps logical to physical

• With MMU, value in relocation register
  added to every address generated by
  user process when sent to memory

• User program deals with logical
  addresses; never sees real physical
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          Dynamic Loading                                     Dynamic Linking
• Routine not loaded until called
                                                   • Linking postponed until execution time
• Better memory utilization; unused routine        • Small piece of code, stub, used to locate
  never loaded                                       appropriate memory-resident library
• Useful if large code for infrequent cases          routine
• No special support from OS –                     • Stub replaces itself with address of
  implemented through program design                 routine, and executes routine
                                                   • OS must check if routine in process’s
                                                     memory space
                                                   • Particularly useful for libraries
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                                                             Overlays for a
                                                          Two-Pass Assembler
• Keep in memory only instructions and
  data needed at any given time
• Needed when process larger than amount
  of memory allocated to it
• Implemented by user, no OS support,
  program design of overlays complex
• Need to recode if more or less memory
      a bad idea, best not resurrected
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                         Swapping                                             Schematic View of Swapping
• Process can be swapped temporarily out of memory to
  backing store, brought back into memory to continue
• Backing store – disk large enough for copies of all
  memory images for all users
• Roll out, roll in – swapping variant used for priority-
  based scheduling algorithms; lower-priority process
  swapped out to load and execute higher-priority process
• Major part of swap time is transfer time; total transfer
  time approx. proportional to amount of memory swapped
• Modified versions of swapping found on many systems,
  e.g., UNIX, Linux, and Windows
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                                                                                        Hardware Support for
        Contiguous Allocation…                                                      Relocation and Limit Registers
• Main memory usually into two partitions:
   – resident OS usually in low memory with interrupt vector
   – user processes in high memory

• Simple allocation
   – relocation-registers to protect user processes from each other,
     and from changing OS code and data
   – relocation register smallest physical address; limit register range
     of logical addresses: all logical addresses < limit register
   – smallest logical address = 0

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                                                                               Dynamic Storage-Allocation
        …Contiguous Allocation
• Multiple-partition allocation                                             How to satisfy a request of size n from a list of free holes
   – Hole – block of available memory; various-sized holes scattered
     throughout memory
                                                                              • First-fit: Allocate first hole that is big enough
   – When process arrives, is allocated memory from hole large
                                                                              • Best-fit: Allocate smallest hole that is big enough; must
     enough to accommodate it
                                                                                search entire list, unless ordered by size. Produces
   – OS maintains information about:                                            smallest leftover hole
     a) allocated partitions b) free partitions (hole)
                                                                              • Worst-fit: Allocate largest hole; must also search entire
       OS               OS                   OS           OS                    list to find largest leftover hole (keep list in size order)
     process 5        process 5         process 5      process 5
                                        process 9      process 9             first-fit, best-fit better than worst-fit in speed, utilization
     process 8                                         process 10

     process 2        process 2         process 2      process 2

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                   Fragmentation                                                                       Paging
• External Fragmentation – total memory space exists to
                                                                            • Logical address space of a process can be noncontiguous; process
  satisfy a request, but isn’t contiguous.
                                                                              allocated physical memory wherever latter available
• Internal Fragmentation – allocated memory may be                          • Divide physical memory into fixed-sized blocks called frames (size
  slightly larger than requested memory; size difference is                   power of 2, typically 512 bytes – 8KB)
  memory internal to a partition, but not being used                        • Divide logical memory into blocks of same size called pages
• Reduce external fragmentation by compaction                               • Keep track of all free frames
   – shuffle memory contents to place all free memory in 1 big block        • To run program of n pages, need n free frames to load program
   – compaction possible only if relocation dynamic (done at                • Set up page table to translate logical to physical addresses
     execution time) – reasonably, anyway                                   • Internal fragmentation
   – I/O problem                                                               – sometimes less than full page needed
       • lock process in memory while waiting for I/O
       • only do I/O into OS buffers                                                           simplified scheme – more in VM

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                                                                                         Address Translation
   Address Translation Scheme
• Address generated by CPU divided into:
   – Page number (p) – used to index into page
     table with base address of each page in
     physical memory

   – Page offset (d) – combined with base
     address defines physical address for memory

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                 Paging Example                                                              Paging Example

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                  Free Frames                                                             Example
                                                                • Machine-code instruction:
                                                                  ld R2, 0(R3)           ; use R3 as address to load to R2
                                                                • Steps to execute (abbreviated):
                                                                   –   program counter (PC) page looked up in page table
                                                                   –   translate PC to physical frame                     memory reference
                                                                   –   fetch instruction                                   always required
                                                                   –   determine needs to access memory                       memory
                                                                   –   calculate effective address (0 + contents of R3)      reference
                                                                   –   look up effective address’s page in page table        needed for
                                                                   –   translate effective address page to physical frame
                                                                   –   fetch data from memory
                                                                   –   store in R2
             Before allocation          After allocation
                                                                                   how can this possibly work?
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    Implementation of Page Table                                             Associative Memory
                                                                • Associative memory – parallel search
• Page table kept in main memory                                                           Page #         Frame #
• Page-table base register (PTBR) points to page table
• Page-table length register (PRLR) has size of page table
• In this scheme every data/instruction access needs 2
  memory accesses: page table and data/instruction
• 2-memory access problem can be solved by special fast-
  lookup hardware cache using associative memory                  Address translation (A´, A´´)
  called translation look-aside buffer (TLB)                      – If A´ is in associative register, get frame # out.
                                                                  – Otherwise
                                                                        • get frame # from page table in memory
                                                                        • add to TLB

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     Paging Hardware With TLB                                              Effective Access Time
                                                                • Associative Lookup = ε time units
                                                                • Assume memory cycle time is 40 nanoseconds
                                                                • Hit ratio – fraction of times page number found in TLB;
                                                                  ratio related to size of TLB, memory access pattern
                                                                • Hit ratio = α                 normal memory reference
                                                                • Effective Access Time (EAT) add 1 extra for page table on TLB miss
                                                                                 EAT = (40 + ε) α + (80 + ε)(1 – α)
                                                                                     = 80 – 40α + ε
                                                                • In practice hits fully pipelined (ε in effect = 0 for hits);
                                                                  real page table takes > 1 extra memory reference on a
                                                                  miss from TLB

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                                                                                 Valid (v) or Invalid (i) Bit
            Memory Protection                                                        in a Page Table
• Memory protection implemented by associating
  protection bit with each frame

• Valid bit in each entry in page table:
   – bit set (1) indicates associated page is in process’s
     logical address space, and is thus a legal page
   – bit 0 indicates page not in process’s logical address
   – here for readability: v = valid, i = invalid

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                      Problem                                                      Page Table Structure
• Address space may be very large, e.g.:                              • Hierarchical Paging
   – 32-bit addresses 4GB
   – 64-bit addresses millions of TB
                                                                      • Hashed Page Tables
• May have big gaps (sparse), e.g.
   – stack grows down from high memory
   – dynamic allocation grows up from low memory                      • Inverted Page Tables

• Page table very large, a lot “invalid”
   – big waste of memory
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      Hierarchical Page Tables                                             Two-Level Paging Example
                                                                  •    A logical address (on 32-bit machine with 4K page size) is
                                                                       divided into:
• Break up logical address space into                                  – page number of 20 bits
  multiple page tables                                            •
                                                                       – page offset of 12 bits (210 = 1K; 212=4K)
                                                                       Since page table is paged, page number further divided into:
                                                                       – a 10-bit page number
                                                                       – a 10-bit page offset

• Simple technique: 2-level page table                            •    Thus, a logical address is split as follows:
                                                                                           page number          page offset
                                                                                               pi       p2           d
                                                                                                1       1            1
                                                                                                0       0            2
                                                                       where pi is index into top-level (“outer” in book) page table, and
                                                                       p2 is displacement within page of top-level page table

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Two-Level Page-Table Scheme                             Address-Translation Scheme
                                                      • Address-translation for 2-level 32-bit paging

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        Hashed Page Tables                                      Hashed Page Table
• Common in address spaces > 32 bits

• Virtual page number hashed onto page
  table: contains chain of elements hashing
  to same location

• Virtual page numbers compared in chain
  searching for match: if match found,
  corresponding physical frame used
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                                                               Inverted Page Table
         Inverted Page Table
• 1 entry for each real page of memory
• Entry is virtual address of page stored in real
  location, with information about owning process
• Decreases memory to store page table,
  increases time to search for page translation
• Hash table limits search to O(1) entries
• Popular with virtual space >> physical
• Hard to handle aliases (> 1 virtual page maps to
  1 physical page)
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                     Shared Pages                                                     Shared Pages Example
• Shared code
   – 1 copy of read-only (reentrant) code shared among processes
     (i.e., text editors, compilers, window systems, shared libraries)
   – shared code must be in same location in logical address space
     of all processes (at least same offset from start of page)

• Private code and data
   – each process keeps separate copy of code and data
   – pages for private code and data can be anywhere in logical
     address space

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                     Segmentation                                                   User’s View of a Program
• Memory-management scheme that supports user view of memory.
• Program is collection of segments. Segment a logical unit such as:
              main program
              local variables, global variables
              common block
              symbol table

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  Logical View of Segmentation                                                   Segmentation Architecture…
                                                                              • Logical address consists of a 2-tuple:
                                                 4                                         <segment-number, offset>,
                                                                              • Segment table – maps 2-dimensional physical
                          2                                                     addresses; each table entry has:
                                                                                 – base – contains starting physical address where segments
             3                                                                     reside in memory
                          4                                                      – limit – specifies length of segment
                                                                              • Segment-table base register (STBR) points to segment
                                                                                table’s location in memory
                                                                              • Segment-table length register (STLR) indicates number
                                                                                of segments used by a program
             user space                physical memory space                     – segment number s is legal if s < STLR

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   …Segmentation Architecture…              …Segmentation Architecture
                                        • Protection: with each entry in segment table:
• Relocation
                                          – valid bit = 0 ⇒ illegal segment
  – dynamic
  – by segment table                      – read/write/execute privileges
                                        • Protection bits associated with segments; code
• Sharing                                 sharing at segment level
  – shared segments                     • Since segments vary in length, memory
  – same segment number                   allocation a dynamic storage-allocation problem
• Allocation                            • Segmentation example: next slide
  – first fit/best fit
  – external fragmentation

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      Segmentation Hardware                 Example of Segmentation

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                                           Segmentation with Paging –
        Sharing of Segments
                                        • MULTICS solved problems of external
                                          fragmentation and lengthy search times
                                          by paging segments

                                        • Solution differs from pure segmentation:
                                          segment-table entry contains not base
                                          address of segment, but base address of
                                          page table for this segment.

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MULTICS Address Translation                       Segmentation with Paging –
        Scheme                                            Intel 386
                                                   • Next slide: Intel 386 and later use
                                                     segmentation with paging
                                                   • OS/2 uses full scheme
                                                   • Other OSes mostly only use pages
                                                       – Portability to other CPUs (Alpha, …)
                                                          • Linux, Windows NT and successors …

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Intel 386… Address Translation                                    Summary
                                                   •   Hardware support
                                                   •   Performance
                                                   •   Fragmentation
                                                   •   Relocation
                                                   •   Swapping
                                                   •   Sharing
                                                   •   Protection

                                              multiple processes create need for managing memory
                                                                – more next time
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             Next week

  • Read Chapter 10
    – Follows closely from this week
  • Assignment 2 to be issued 30 April
    – memory and storage management
      (most likely VM)

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