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					                                         MIKE NICHOLAS
                                            Southampton.
                                           Hampshire. UK


       Personal Profile

A reliable and confident worker who has spent the last 10 years in the microchip design industry. I am
extremely adaptable when taking on new jobs which require a fast learning curve. A good team
member who works well under pressure and enjoys a challenge.

       Key Skills

   Microchip design. Experienced with many software packages used in the design process. Helped
    design many microchips which have gone into mass production. My key work areas have been
    Design-For-Test (DFT), Static Timing Analysis (STA), Formal Verification and IP integration. A
    couple of the chips I worked on were SAA7164 (personal video recorder chip) and PNX8543 (set
    top box video chip).
   Software installations on a Linux based system.
   Programming in low level C/C++ and scripting languages such as TCL, Perl and Csh.
   Technical report writing.
   Familiar with Microsoft packages such as Word, Excel, and Powerpoint.
   Experienced in solving manufacturing problems.
   Know how to run a small company. Familiar with the finance and administration side of things.

         Education and Training

Jul 09   -> Conformal (Cadence) update seminar from a leading expert.
Mar 07   -> Synopsys Primetime update seminar, 1 day.
Dec 06   -> Synopsys seminar on power saving techniques, 1 day.
Mar 03   -> Overview of Synopsys latest design-for-test (DFT) offerings, 1 day.
Jul 02   -> PrimeTime-SI (Signal Integrity) at Synopsys, 1 day.
Jul 02   -> PrimeTime (Static timing) at Synopsys, 2 days duration.
Jun 02   -> Advanced Chip Synthesis (not physical synthesis) at Synopsys, 3 days.
Jun 02   -> DFT Compiler + Tetramax (Synopsys test pattern generator), 4 days onsite training.

1994 – 1998      Staffordshire University, UK
       MEng (Masters) and BEng in Micro-electronics and computer engineering.
        Final year project was to implement a modem in software using a digital signal processor.

1992 – 1994    Burton Upon Trent technical college, UK
       OND in Electrical and electronic engineering.

         Career summary
NXP Semiconductors, Southampton, UK
January 6th 2009 – Dec 24th 2009 (11.5 month contract)
Computer Aided Engineer
 Synthesis and scan insertion flow development (Cadence).
 C++ software development using a netlist manipulation tool called Verific.
 Tool installations (Cadence, Mentor, etc) and general support.

NXP Semiconductors, Eindhoven, The Netherlands
February 13th 2008 – Nov 12th 2008 (9 month contract)
Synthesis & STA Consultant
 IP integration, synthesis (Cadence) and timing constraint development (ets). 45nM design.
NXP Semiconductors, Southampton, UK
July 16th 2007 – Feb 4th 2008 (6.5 month contract)
Integration Engineer
 IP integration involving scan insertion (Synopsys), Test coverage analysis and Formal verification.

NXP (formerly Philips Semiconductors), Eindhoven, The Netherlands
November 20th 2006 – July 12th 2007 (8 month contract)
Synthesis & STA Consultant
 Timing constraint development (PrimeTime). 65nM design.

Philips Semiconductors, Hamburg, Germany
September 6th 2005 – November 16th 2006 (14 month contract)
Timing Verification Engineer
 Chip/Block level test constraint creation and STA using PrimeTime.
 2 proven tapeouts on a large successful 90nM multimedia audio/video SOC design containing
    2.5 million instances and 450K flops.

Philips Semiconductors, Southampton, UK
March 2nd 2005 – September 2nd 2005 (6 month contract).
Integration Engineer
        IP integration involving scan insertion, Formal verification and Synthesis. 90nM design.

intel, Braunschweig, Germany
August 18th 2004 – February 18th 2005 (6 month contract).
Synthesis and Verification Engineer
       Block level synthesis, Static Timing and DFT on a 90nM multi-million gate design.

Philips Semiconductors, Southampton, UK
May 27th 2004 – August 12th 2004 (2.5 month contract).
Intellectual Property (IP) Integrator
         Complex test/glue logic creation (VHDL), Synthesis and Simulation using NCSIM.

Sci-worx (Infineon), Hannover, Germany
January 12th 2004 – April 9th 2004 (3 month contract)
Implementation Engineer
        USB2.0 Project (0.13). Synthesis & DFT. Close contact with layout.

Zarlink Semiconductor (formerly Mitel Semiconductors), Swindon, UK.
January 10th 2000 – September 12th 2003 (redundancy)
Computer Aided Engineer
        Primary support contact for a selection of design flow tools which included Voltagestorm
         (transistor level), NCSIM, AMS designer, and Logicvision. Some ASIC implementation.

GAI-tronics Ltd, Burton Upon Trent, UK
June 28th 1998 – December 30th 1999
Application Engineer
        Product support which involved working at circuit level and extensive use of Autocad Lt97
         package. Was also involved in design for EMC compliance.

         Personal details
Date of Birth:            16th April 1976, British Citizen
Health:                   Exercise regularly, non-smoker.
Licence:                  Car owner with full UK drivers licence.
References:               Available on request.
Personal Interests:       I have a keen interest in most sports.

				
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