The Interaction of Simultaneous Multithreading processors and the

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					The Interaction of Simultaneous
Multithreading processors and
the Memory Hierarchy:
some early observations

           James Bulpin
       Computer Laboratory
      University of Cambridge
Simultaneous Multithreading
   An extension to dynamic out-of-order
    superscalar processors
   Very fine grain hardware multithreading
   Converts thread level parallelism into
    instruction level parallelism
       Latency hiding
       Functional unit utilisation
   Mutual effect of threads
Intel® Hyper-Threading®
   First commercial implementation of SMT
   2 heavyweight threads
   Combination of static and dynamic
    sharing of resources
   Now standard on desktop and newer
    mobile Pentium 4 chips
   Originally marketed as two processors
    for the price of one
Multiprogramming Performance
   SPEC CPU2000 benchmark
   Run cross-product of pairs
   Compare to non-SMT and to SMP
   Use processor performance counters
Memory hierarchy interactions
Better latency hiding => more tolerant
  of cache misses
Cooperating threads can share data in a
  common cache
 Multiple threads, shared cache =>
  more cache contention
  • Want to avoid thrashing
  • No explicit partitioning
How can the OS help?
   Avoid inter-thread aliasing
       Linux offset user stacks
   Use cunning page placement
       Try to ensure core “critical” working set stays
        resident in the (L2) cache [Lo ISCA 98]
   Know when you’re fighting a losing battle
       Back off to single threaded execution
The Plan
   Currently using processor performance
    counters to influence scheduling
   Want to use performance counters and
    statistics from OS memory management
    to influence page placement
       Keep virtual addressing abstraction for
       Support legacy applications

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