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# Fault Model Single Stuck at Fault Design Representation by fdjerue7eeu

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```									     Fault Model: Single Stuck at
Fault
Design Representation level:
Gate Level
Single Stuck at 0 or 1 Fault

X1
G1
G5
X2
G3
X3
G2
X4                                  G6
G4
X5
How to Detect a Fault

Stuck at 1 Fault

X1
G1
G5
X2
G3
X3
G2
X4                           G6
G4
X5
Step #1: ‘Controlability’
Stuck at 1 Fault

X1
G1
G5
X2
G3
X3
G2
X4                                      G6
G4
X5

Sensitize fault - control input path to fault
Step #1: ‘Controlability’
Stuck at 1 Fault
Fault ckt: 1
X1   1
correct ckt: 0
G1
G5
X2
1                     G3
X3
G2
X4                                          G6
G4
X5

Sensitize fault - control input path to fault
Step #2: ‘Observability’
Stuck at 1 Fault
1
X1
G1
G5
X2
G3
X3 1
G2
X4                                         G6
G4
X5

Propagate ‘fault’ to output pin
Step #2: ‘Observability’
Stuck at 1 Fault

X1 1                                                    Observe fault
G1
G5          0 : faulty ckt
X2     0                             1                   1 : correct ckt
G3
X3 1                  -
G2
X4 -                                  -      G6
G4                        -
X5 -

Propagate ‘fault’ to output pin
Detect a different fault
Stuck at 0 Fault

X1
G1
G5
X2
G3
X3
G2
X4                           G6
G4
X5
Simplify this process by
detecting stuck at D fault
Stuck at D Fault
D
X1                                ¯
D
G1                                        D
G5
0
X2                                    1
1                      G3
X3                    -
-       G2                                    -
X4                                    -      G6
-                        G4
X5
Test Pattern                                   Test Response

Test Vector is (input stimulus , output response)=(D 0 1 - - D -)=
((0 0 1 - - 0 -) (1 0 1 - - 1 -))=((0 0 1 0 0 0 0)(1 0 1 0 0 1 0))
X1 X2 X3 X4 X5 Z1 Z2 Stuck at Faults detected on wires
D 0 1 - - D -           x1,a
- D 0 0 - D -           x2,b
- 1 D 1 0 - db         x3,c,d,z2
- 0 0 - D - D           x5,d,z2
- 0 1 D 1 - db         x4,c,d,z2

X1                         a
G1                                    Z1
G5
X2                                   b
G3
X3                    c
G2                                   Z2
X4                                  d      G6
G4
X5
Undetectable fault ...
SSA-D fault

D               D

1                              D

0?                    D                   ?

1?
1

Need to set this wire to 1 for observability
and 0 for controlability
FF                FF        FF

CL            CL

FF                FF        FF

Scan Chain
Random Patterns and Fault
Coverage
100%

Fault Coverage

Number of Pseudorandom patterns

```
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