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LAB 3 A simple CPU in VHDL

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LAB 3 A simple CPU in VHDL Powered By Docstoc
					LAB 3
                              A simple CPU in VHDL


Objective
This objective of this laboratory experiment is to design and build a very simple CPU in
VHDL.


Upon completion of this laboratory, the student should be able to:
   •   Design and build all functions of a simple CPU.
   •   Design, simulate and program a simple CPU using VHDL on an Altera UP2
       board
   •   Output the results on the LCD Display


PreLab
   •   Read section 6.6.8 of your textbook.
   •   Write a VHDL code for a 4-bit D-flipflop using the 1-bit D-flipflop you designed
       in Lab1 as a component. Refer to the VHDL code in your book figures 5.22 and
       5.23 for the use of components.
   •   Write a VHDL file that acts as a feeder for UP3_LCD block. This block
       (feeder.vhd) has two 8-bit inputs which are the BCD representations of the A and
       B inputs of your ALU. The feeder’s 80-bit output to the UP3_LCD should consist
       of the two BCD values of A and B. The LCD should display the following:
       “#valueOfA #ValueOfB”
   •   Design all functions of the ALU in VHDL as describe in part2 (Refer to figure
       6.48 of your book).


   Note: Most of your design should be completed prior to the Lab session. Do not waste
   your lab time designing the ALU and the other components, but rather testing it with
   the Altera FPGA. Be ready to show the TA your code, as well as answering questions
   regarding the prelab.
Part1: Acquiring multiple data from same DIP switch


       The ALU performs a set of functions on two 4-bit inputs (A and B). In our design,
these values must be set by the user and changed dynamically at wish. We are faced with
the problem of having one 4-bit DIP switch available to us on the UP3 board. We thus
have to find a way to use the same DIP switch for multiple data acquisitions. In lab1 you
were asked to design a 1-bit D-flipflip. D-flipflops can act as simple storage units that are
loaded whenever the clock input is on rising edge.


                        Push
                       Buttons




                                           A3
                                           A2
                                           A1
                                           A0
                      Storage                                  Display
                       Unit                                     Unit           LCD
     DIP                                                                      Display
    Switch

                                           B3
                                           B2
                                           B1
                                           B0


                          Figure 1: Part1- Data Acquisition and Display

       The Display Unit is responsible for outputting the proper format for the LCD
display. Note that the 8-bits fed from the storage unit need to be converted to BCD
format before being concatenated and inputted to the UP3_LCD.
After completing the design follow these steps:
   1. Import and assign all pins. Refer to the UP3 manual, lab1, and lab2.
   2. Compile, simulate, and test your design.
   3. Burn the program on the UP3 board. You can input a value on the DIP switch and
       press the appropriate push button to load into the right register. The values should
       be visible to you on the LCD as they change.
   4. Show your TA the working program.
Part2: A simple ALU:

       The CPU of a computer is usually divided into at least four components, the
control unit which performs the fetch/execute cycle, the bus unit which controls access to
the data and address bus, internal registers for temporary storage, and the
arithmetic/logic unit (ALU) that performs arithmetic and logical operations. In this
laboratory we will focus on the Arithmetic Logic Unit (ALU). The ALU will be tested by
performing the arithmetic for a simple calculator.
   The heart of every computer is an Arithmetic Logic Unit (ALU). This is the part of
the computer which performs arithmetic operations on numbers, e.g. addition,
subtraction, etc. In this lab you will use VHDL to implement an ALU with eight
functions.
   •   The ALU must consist of two 4-bit input values and a 3-bit select input that
       chooses which operation is to be performed on the two values, as shown below:
   •   Your ALU will perform eight functions on two 4-bit inputs (A and B). These
       inputs could represent either unsigned numbers (need carry-out), two's
       complement numbers (need overflow), or simply bit patterns. The ALU will
       generate a 4-bit output (R), a carry, and an overflow.
   •   To select which of the eight functions to implement you will need three select
       inputs. A block diagram is shown in Figure 1.




                               Figure 2: Block diagram of ALU
   •   There is a 4-bit output R, which gives the result of the operation specified on the
       two input values, and a 1-bit Cout output used to detect an overflow or underflow
       condition.
   •   The encoding of the three select bits tells the circuit what operation to perform on
       the two input according to the following table:


                Control Inputs    FUNCTION         OUTPUT             EXAMPLES

                     (S2 S1 S0)                                     (A3A2A1A0,
                                                                B3B2B1B0, R3R2R1R0)
                        000           ADD         A+B           A=0010, B=0100,
                                                                R=0110,Cout=0

                                                                A=1100, B=1000,
                                                                R=0100,Cout=1
                        001           AND         A AND B       A=0010, B=0011,
                                                                R=0010
                        010           XOR         A XOR B       A=0010, B=0011,
                                                                R=0001
                        011            OR         A OR B        A=0010, B=0011,
                                                                R=0011
                        100           NOR         A NOR B       A=0010, B=0011,
                                                                R=1100
                        101           SUB         A–B           A=0010, B=0011,
                                                                R=0001,Cout=1

                                                                A=0100, B=0001,
                                                                R=0011,Cout=0
                        110           SRL         Shift A to    A=1100, B=0010,
                                                  the right     R=0011
                                                  by B bits
                                                                A=0011, B=0001,
                                                                R=0001
                        111           SLL         Shift A to    A=1100, B=0010,
                                                  the left      R=0000
                                                  by B bits
                                                                A=0011, B=0011,
                                                                R=1000

                                  Table 1: Control inputs functions


Design restriction

   •   Implement your design using VHDL code only.
   •   Use graphic symbols only for the top-level final implementation.
   •   Use of the "CASE" structure will make this job easy (Not mandatory).
   •   Cout is only valid for the ADD and SUB functions. For all others, Cout should be
    0 regardless of the two inputs.
•   The logical functions (AND, XOR, OR, and NOR) should be performed bit –by-
    bit on each input (e.g. if the function is A XOR B, the answer is Ro=Ao XOR Bo,
    A1 XOR B1, A2 XOR B2, A3 XOR B3).
•   The shift functions (SRL and SLL) may cause 1’s to drop off the end as shown in
    the example above, and 0’s are shifted in the other side. There is no wrap-around
    for those functions (that is, if you right-shift 0011 by 2 the answer is 0000, not
    1100). SRL=shift right logical, and SLL= shift left logical.
•   To the external world, the addition and subtraction performed by your unit are
    unsigned. So none of the four bits of A, B or R are always positive. If an addition
    of two numbers is greater than 15, the answer you display is the real result minus
    16, and set the carryout bit to be a 1 indicating an overflow.
•   Simulate all the ALU functions, and check your results with the expected values
    for:
                        A =1111 and B =0010.
                        A =1001 and B =0111.
•   The result of the ALU is passed through the display unit. The LCD should display
    the following: “#valueOfA #ValueOfB #ValueOfResult”
•   The select inputs of the ALU are 3 bits whereas we store 4 bits from the input
    value on the DIP switch. We drop the most significant bit and only take the least
    3-bits of the vector.
•   You will need to use an extra push button to store the select inputs.
•   Compile, simulate, and test your design.
•   Burn the program on the UP3 board. You can input a value on the DIP switch and
    press the appropriate push button to load into the right register. Do this three
    times for A, B, and the select inputs S. The LCD should display the values of A,
    B and the Result of the ALU operation.
•   You must demonstrate a working system to the TA.
In your report you must:


   •   Include timing simulation with explanation for all VHDL files.
   •   Describe and comment on all your VHDL files.
   •   Include the state diagram with explanation of your design.
   •   Include a flow diagram with explanation of your design.
   •   A brief description of your design problems and solutions.
   •   Include a copy of you files in your report.
   •   Include a copy of your design on a floppy disk
   •   Refer to the marking scheme on you course webpage for further requirements.

				
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