ELEC 5705 Synthesizer Integrated Circuit Design
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ELEC 5705 Synthesizer Integrated Circuit Design: Assignment #3 Due March 31. 2005 before class at 7:30pm The goal of this course will be to design using Cadence Design Systems a completely integrated frequency synthesizer. The third assignment will be to design the PFD and CP and implement them at the transistor level. A rough guide for the synthesizer specs will be as follows: - Center Frequency of the VCO: 5GHz - Tuning Range: 4.8GHz – 5.2GHz - KVCO: 135MHz/V - Divide Ratio 110-140 (large enough to lock the VCO over its whole range) - XTAL frequency: 40MHz - Divide ratio programmable in steps of 1. - Supply voltage will be 3V For this assignment complete the following: 1) Design a transistor level PFD and CP. The PFD the circuit on page 39 of Ch6 is preferred. The CP should be designed for best noise operation and the PFD should be current optimized. 2) Show the circuits working in the loop with the divider from assignment #2. Note you may use a much larger loop BW than 150kHz for this simulation. 3) Include a refined PN estimate at this stage of the design including advice about where the loop BW should be set. 4) Implement the five-state PFD discussed in class using ahdl only, correcting the errors in the circuit in the notes. Compare settling times with the previous system level simulations from assignment #1. All blocks can be ideal here. 5) Using all ideal blocks simulate the effect of a 15% current mismatch in up and down currents from the CP. A dft of the VCO output at full frequency is required, but the divider may be ideal. You may use a larger loop bandwidth here as well. Note: Assignments should be no more than 15 pages in length!