Serial ATA Revision 2.5 Technical Errata Change ID 0018 Applicable Spec. Serial ATA 2.5 Submission info Name Company Date Harvey Newman Infineon Technologies July 28, 2006 Description of the specification technical flaw The definition of a lone bit is not satisfied by the pattern described in the specification. The pattern produces a lone one per this definition but not a lone zero. There is no lone zero prefixed by four ones and suffixed by three ones. There is a lone zero in this pattern that is prefixed by a 10 bit sequence than contains 8 ones and only 2 zeros. This represents the greatest imbalance 8B/10B coding allows. Anywhere rise time limitations prevent maximum amplitude from being reached in one half unit interval this sequence will cause the lone zero amplitude to be reduced. The defined pattern is not disparity agnostic. This means when D12.0 and D10.4 are applied to the 8B/10B encoder two different patterns are produced based on the starting running disparity of the encoder. One of these possible patterns does not contain any lone bits. Since there is no way to determine or set the starting running disparity there is a 50% chance the pattern produced contains no lone bits and measurements can not be performed. By changing the second D11.4 to D11.3 the final bit in the sequence is toggled which causes the starting running disparity to alternate and guarantee the lone bit pattern. Description of the correction: Section 22.214.171.124.5 The lone-bit patterns, shown in Figure 92 and Figure 93, are comprised of the combination of adjacent 10B patterns, resulting in a lone one bit prefixed by a run length of four zeros, and suffixed by a run length of three zeros. It also results in a lone zero bit prefixed by a run length of two ones, one zero, two ones, one zero, four ones, and suffixed by a single one. LBP Starting with RD– Transmission order - D12.0(0Ch)- D11.4(8Bh)+ D12.0(0Ch)- D11.3(6Bh)+ + 0011 0110 1111 0100 0010 0011 0110 1111 0100 0011 3 6 F 4 2 3 6 F 4 3 + D12.0(0Ch)+ D11.4(8Bh)- D12.0(0Ch)+ D11.3(6Bh)- - 0011 0101 0011 0100 1101 0011 0101 0011 0100 1100 3 5 3 4 D 3 5 3 4 C Figure 92 – Lone-Bit Pattern (LBP) starting with RD– Long version total: 1 * 2048 = 2048 Dwords Short version total: 1 * 128 = 128 Dwords LBP Starting with RD+ Transmission order + D12.0(0Ch)+ D11.4(8Bh)- D12.0(0Ch)+ D11.3(6Bh)- - 0011 0101 0011 0100 1101 0011 0101 0011 0100 1100 3 5 3 4 D 3 5 3 4 C - D12.0(0Ch)- D11.4(8Bh)+ D12.0(0Ch)- D11.3(6Bh)+ + 0011 0110 1111 0100 0010 0011 0110 1111 0100 0011 3 6 F 4 2 3 6 F 4 3 Figure 93 – Lone-Bit Pattern (LBP) starting with RD+ Long version total: 1 * 2048 = 2048 Dwords Short version total: 1 * 128 = 128 Dwords Section 126.96.36.199 e) The lone-bit patterns (LBP) are comprised of the consecutive combination of certain 10b patterns that result in a lone-bit. More specifically, a lone-bit is prefixed by a run-length of four bits and followed by a run-length of three or prefixed by a run length of two ones, one zero, two ones, one zero, four ones, and suffixed by a single one. These patterns create a condition where the preceding 4-bit run-length results in minimum amplitude of the lone-bit as well as its time-width in comparison to its surrounding segments. This is often the worst case condition that the receiving data recovery circuits may encounter. Disposition log 7/28/2006 Initial release 7/28/2006 Added change to section 188.8.131.52 & errata # 7/31/2006 Changed ending disparity on first line of RD+ 8/2/2006 Approved by SATAIO Phy WG Technical input submitted to the Serial ATA International Organization is subject to the terms of the SATA-IO contributor’s agreement.