TECHNICAL FEATURE AVE JOU OW R RN MIC AL REVIEWED D ED IT R OR A IAL B O EFFECTIVE CIRCUIT DESIGN TECHNIQUES TO INCREASE MOSFET POWER AMPLIFIER EFFICIENCY N ewly developed low cost and highly percent idealized drain efficiency must be1 linear, high gain and high power later- ally diffused metal oxide semi-conduc- 8 Eds Z1 = R 1 = , tor (LDMOS) and vertically diffused metal ox- π Is ide semiconductor (VDMOS) field-effect Zn = 0 Ω for even n, transistors are attractive devices for many ap- plications including commercial FM broad- Zn = ∞ Ω for odd n, (1) casting and TV power transmitters, cellular and paging communication systems, and mili- where tary RF and microwave hand-held trans- Eds = drain supply voltage ceivers. In all cases, along with high quality Is = peak drain current transmission of radio signals resulting from n = harmonic component the high linearity of the amplifier transfer characteristic, it is necessary to provide high These impedance conditions correspond to reliability and low overall dimensions of the the class F operating condition, the ideal voltage power amplifiers along with an increase in to- and current shapes for which are shown in Fig- tal operating efficiency. ure 1. Here a sum of odd harmonics produces a Fig. 1 Ideal class To obtain high efficiency of the power ampli- square voltage waveform and a sum of even har- F voltage and fier, it is advisable to use a tuned class B or Class monics approximates a half-sinusoidal current current waveforms. w shape. In reality, both extrinsic and intrinsic tran- F operating mode. 1,2 In such amplifiers, the fundamental and sistor parasitic elements have a substantial effect harmonic load impedances are on the efficiency, especially at high frequencies. Eds By using only the active device die it is possible optimized by short-circuit termi- to reduce the influence of the parasitic elements Vds nations and open-circuit peaking in order to control the voltage in the power amplifier module. However, in this and current waveforms at the case it is necessary to take into account the main Is drain of the device to obtain influence of the device output capacitance Cout. maximum efficiency. Ids CLASS F OPERATION ANDREY V. GREBENNIKOV TIME (t) The impedance conditions at Institute of Microelectronics the drain of the device for 100 Singapore Reprinted with permission of MICROWAVE JOURNAL® from the July 2000 issue. © 2000 Horizon House Publications, Inc. TECHNICAL FEATURE Eds The ideal class 12.8 nH, C2 = 5.3 0 Cbypass F amplifier with a pF) with a quality voltage second- factor Q of 20 for −10 harmonic short- the inductances at S21 (dB) circuit termination the fundamental −20 L2 C2 and current third- frequency f = 0.5 harmonic peaking GHz, and a device −30 allows realization output resistance of the maximum Rout of 200 Ω and −40 L1 0 0.5 1.0 1.5 2.0 2.5 drain efficiency of output capacitance FREQUENCY (GHz) 75 percent.3 For a C out of 2.2 pF is TO OUTPUT lumped-circuit shown in Figure v Fig. 4 The lumped impedance peaking Rout Cout Yout MATCHING amplifier, in order 4. To increase the circuit’s frequency response. CIRCUIT to approximate total efficiency of Fig. 5 The microstrip amplifier’s output ideal class F oper- the amplifier, the impedance peaking circuit. w v Fig. 2 An output impedance ation with the har- element of the out- peaking circuit. Eds monic impedance put matching cir- conditions of Z1 = cuit adjacent to the Cbypass Fig. 3 The two-port passive circuit’s Z3 = ∞ Ω and Z2 = drain of the tran- schematic for simulation. w 0 Ω at the drain by sistor must be se- θ1 θ2 d d compensating for ries and inductive IMPEDANCE the influence of in order to provide θ2 INPUT PEAKING OUTPUT CIRCUIT Cout it is advisable a high impedance TO OUTPUT to use an addition- for odd harmonic Rout Cout MATCHING CIRCUIT al parallel circuit. components.1 An equivalent output impedance peaking circuit for a To increase lumped-circuit amplifier is shown in Figure 2. The reac- maximum drain ef- tive part of the output admittance of this circuit is given ficiency up to 88.4 Fig. 6 The microstrip impedance forming by percent, it is nec- circuit’s frequency response. w essary to provide a 0 1 – ω 2L 2C 2 ( ) Im Yout = jω Cout – j short-circuit termi- ( ) (2) ω L 1 1 – ω 2L 2C 2 + ωL 2 nation for all even- −10 harmonic voltages S21 (dB) and an open-cir- −20 Applying the previously mentioned three harmonic im- cuit impedance for pedance conditions, open-circuited for the fundamental third-harmonic −30 and third harmonic and short-circuited for the second currents.3 Class F harmonic, equation (2) can be rewritten in the form operation mode is −40 ( )( ) 0 0.5 1.0 1.5 2.0 2.5 1 – ω 2L C easy to realize by 0 1 out 1 – ω 0 L 2 C 2 – ω 0 L 2 Cout = 0, 2 2 FREQUENCY (GHz) using transmission ( L 1 1 – 4 ω 0 L 2C 2 + L 2 = 0, 2 ) (3) lines in the output circuit. For a microstrip amplifier, it is enough to provide transmission lines with electrical ( )( ) lengths at the fundamental frequency of 1 – 9ω 0 L 1Cout 1 – 9ω 0 L 2C 2 – 9ω 0 L 2Cout = 0 2 2 2 π 1 1 π θ1 = , θ 2 = tan –1 , θ3 = (5) where 2 3 3Z0 ω 0Cout 6 ω0 = 2π f0 f0 = fundamental frequency where As a result, the elements of the output impedance Z0 = characteristic impedance of the microstrip line peaking circuit are The equivalent output impedance peaking circuit of microstrip amplifier is shown in Figure 5. The frequency- 1 5 12 response characteristic of the microstrip impedance-form- L1 = , L2 = L1, C2 = Cout (4) 6 ω 0 Cout 2 3 5 ing circuit on a substrate with dielectric loss tangent tan δ = 0.0001 featuring a device output resistance Rout of 50 Ω Linear analysis, which is sufficient to compute the re- and an output capacitance Cout of 2.2 pF, with a charac- sponse of a two-port passive circuit with lumped or distrib- teristic impedance of the microstrip lines Z0 of 50 Ω and uted parameters, has been accomplished using the Sere- electrical length θ2 of 15° is shown in Figure 6. It follows nade 7.5 CAD simulator. Simulations were performed ac- from the data that if the short-circuited conditions for all cording to the schematic shown in Figure 3 regarding the even voltage harmonics and current third-harmonic peak- drain of the device. The frequency-response characteristic ing are in place, then additional output matching is re- of a lumped impedance-peaking circuit (L1 = 7.7 nH, L2 = quired at the fundamental frequency f0 = 0.5 GHz taking TECHNICAL FEATURE 24 V + − 58.7 pH 13.7 Ω 0.029 pF 9.1 Ω 100 pF G D 1.5 kΩ 4.5 nH 56.9 pH 0.73 pF 300 Ω 10 pF 0.31 pF 1.2 Ω 500 Ω 3.6 nH 0.28 pF τ = 14.1 ps 0.87 Ω 0.26 pF 2 pF 25 nH 15 nH 3.5 pF gm = 21.1mS Rds = 4.37 kΩ Pout 1.0 pH Pin 6 pF 1.1 pF S S v Fig. 8 The simulated 500 MHz one-stage lumped power v Fig. 7 The LDMOS FET’s small-signal equivalent circuit. amplifier’s equivalent circuit. into account the reactance intro- 100 22 100 22 duced by the impedance peaking EFFICIENCY (%) EFFICIENCY (%) 80 20 80 20 circuit. GAIN (dB) GAIN (dB) 60 18 60 18 AMPLIFIER NONLINEAR CAD 40 16 40 16 SIMULATION 20 14 20 14 The small-signal equivalent circuit 0 12 0 12 10.0 15.0 20.0 25.0 10.0 15.0 20.0 25.0 of a high-power LDMOS FET cell Pin (dBm) Pin (dBm) with channel length L = 1.25 µm and channel width W = 1.44 mm is shown v Fig. 9 Drain efficiency and gain v Fig. 11 Drain efficiency and gain in Figure 7. The device model para- vs. input power. vs. input power when the inductances meters were extracted from pulsed I- have a Q of 30. V and S-parameter measurements. Fig. 10 The drain voltage waveform The parameters of the equivalent cir- approximation. w 60 cuit are given at a bias voltage for 60 class AB operation with quiescent 40 Vds (V) current Iq = 15 mA at Eds = 28 V. 40 Vds (V) The equivalent circuit of the simu- 20 lated 500 MHz one-stage lumped 20 power amplifier is shown in Figure 0 0 1 2 3 4 8. The total channel width of the high-voltage LDMOS FET is 7 × 0 0 1 2 3 4 TIME (ns) 1.44 mm. The drain efficiency and TIME (ns) v Fig. 12 The microstrip amplifier’s drain gain of the amplifier versus input voltage waveform. power Pin for the case of ideal circuit circuits based on microstrip lines. In inductances are shown in Figure 9. a simulated 500 MHz one-stage mi- Fig. 13 The microstrip amplifier’s drain The obtained value of the drain effi- crostrip power amplifier, the input efficiency and gain vs. input power. w ciency of more than 80 percent is the and output matching circuits are T- 100 22 result of additional harmonic peaking section matching circuits, and each of EFFICIENCY (%) them consists of a series microstrip 80 20 on higher components which allows a GAIN (dB) shortened switching time from the line, parallel open-circuit stub and se- 60 18 pinch-off region to the saturation re- ries capacitance. To provide even har- 40 16 gion by better approximation of the monic termination and third-harmon- 20 14 drain voltage square waveform, as ic peaking for class F operation, an 0 12 shown in Figure 10. However, the RF short-circuited quarter-wave mi- 10.0 15.0 20.0 25.0 amplifier drain efficiency as well as crostrip line and combination of se- Pin (dBm) the gain can reduce significantly in ries microstrip line and open-circuit the case of sufficiently small values of stub of λ/12 electrical length for third shown in Figure 13. The power am- a circuit inductance Q. For example, harmonic termination are used. Such plifier’s equivalent circuit is shown in the maximum drain efficiency is only an output circuit configuration close- Figure 14. 71 percent when an inductance Q of ly matches the square drain voltage However, a further increase of the 30 at the fundamental frequency is waveform, as shown in Figure 12 total LDMOS FET channel width used, as shown in Figure 11. and a high value of drain efficiency leads to an increase of Cout and, as a Therefore, for high output power up to 80 percent with maximum out- result, to a decrease in electrical level, it is preferable to use matching put power Pout = 9 W is obtained, as length of the series microstrip line TECHNICAL FEATURE 100 22 28 V EFFICIENCY (%) 80 20 +− GAIN (dB) 60 18 1.5 kΩ 40 16 100 pF 300 Ω 20 14 0 12 30 Ω 0 5 10 15 20 25 30 30 Ω 500 Ω 65 ° Pin (dBm) 30 Ω 2 pF 54 ° 58 ° 9 pF v Fig. 16 Drain efficiency and gain Pout vs. input power for the T-section impedance. Pin 50 Ω 50 Ω 63 ° 46 ° Fig. 17 Drain voltage and current waveforms using the T-section impedance matching configuration. w v Fig. 14 The simulated 500 MHz one-stage microstrip power amplifier’s schematic. 60 6 28 V 40 4 +− Vds (V) Ids (A) 20 2 1.5 kΩ 100 pF 0 0 300 Ω −20 −2 30 Ω 0 1 2 3 4 30 Ω 500 Ω 65 ° TIME (ns) 30 Ω 2 pF 54 ° 58 ° 9 pF Pout impedance is sufficiently small at the third harmonic. At the same time this Pin 50 Ω 50 Ω 63 ° 46 ° output circuit configuration accom- plishes effective fundamental impe- v Fig. 15 The equivalent circuit of the simulated 500 MHz one-stage microstrip high-power dance matching of the output transis- amplifier using an LDMOS FET with a channel width of 28 × 1.44 mm. tor impedance with the load. adjacent to the drain, the value of mum value. On the other hand, when EXPERIMENTAL RESULTS which becomes too small to provide the transistor is turned off, the drain The experimental test structure of appropriate third harmonic peaking. current continues to flow, but now a single-stage LDMOS FET power In this case, in order to realize both only through the shunt output capaci- amplifier with a device gate length of high efficiency and high power oper- tance Cout. The appropriate required L = 1.25 µm and total gate width of ation, the output circuit must be sim- reactive harmonic load impedance of W = 4 cm is shown in Figure 18. plified to only a T-section for impe- the external circuit is realized by the Two T-section transformers with se- dance matching. The equivalent cir- open-circuit stub at the second har- ries microstrip lines and parallel vari- cuit of the simulated 500 MHz monic whose electrical length is ap- able capacitors have been used as the one-stage microstrip high-power am- proximately 0.125λ and by the RF input and output matching circuits. plifier with a total LDMOS FET short-circuit microstrip line whose The matching circuits were fabricat- channel width W = 28 × 1.44 mm is shown in Figure 15. As it turned out, a significant improvement of drain ef- 3.6 V 28 V ficiency up to 78 percent for an out- put power of approximately 30 W can 18 kΩ 0.1 µF 0.1 µF 10 µF be realized by using the specific elec- + trical length (less than quarter-wave length) of parallel microstrip line, as 1 kΩ 50 Ω shown in Figure 16. Furthermore, 50 Ω 45 ° 50 Ω the analysis of the drain voltage and 6 pF 35 ° 35 ° 9 pF current waveforms, shown in Figure Pin Pout 17, demonstrates that the operating 8.5 TO 40 pF 4.5 TO 20 pF mode obtained is close to class E op- eration mode.5 As seen in the data, when the transistor is turned on, there is practically no voltage when the drain current achieves its maxi- v Fig. 18 The single-stage LDMOS FET power amplifier’s experimental test structure. TECHNICAL FEATURE input and output matching circuits Amplifier,” IEEE Trans. Electron Devices, was required to realize excellent elec- Vol. 14, December 1967, pp. 851–857. 100 22 2. H.L. Krauss, C.W. Bostian and F.H. Raab, trical characteristics of the given LD- Solid State Radio Engineering, New York: EFFICIENCY (%) 80 20 MOS FET power amplifier. Wiley, 1980. GAIN (dB) 60 18 The drain efficiency and power 3. F.H. Raab, “Class-F Power Amplifiers with 40 16 gain characteristics as a function of in- Maximally Flat Waveforms,” IEEE Trans- actions on Microwave Theory and Tech- 20 14 put power are shown in Figure 19. niques, Vol. 45, November 1997, 0 12 An output power of 20 W max with a pp. 2007–2012. 0 5 10 15 20 25 30 drain efficiency of 76 percent and DC 4. C. Duvanaud, S. Dietsche, G. Pataut and J. Pin (dBm) collector current of 0.94 A has been Obregon, “High-efficient Class F GaAs achieved. A practically constant small- FET Amplifiers Operating with Very Low Bias Voltages for Use in Mobile Tele- signal power gain of approximately 17 v Fig. 19 Measured drain efficiency dB was achieved over a wide dynamic phones at 1.75 GHz,” IEEE Microwave and Guided Wave Letters, Vol. 3, August and gain vs. power input. range up to an input power of 25 dBm 1993, pp. 268–270. as a result of the appropriate choice of 5. T.B. Mader, E.W. Bryerton, M. Markovic, ed on epoxy glass copper-clad lami- M. Forman and Z. Popovic, “Switched- nate substrates and the characteristic gate bias voltage. mode High-efficiency Microwave Power impedance of all microstrip lines is Amplifiers in a Free-space Power-combin- equal to 50 Ω. To avoid low-frequen- ACKNOWLEDGEMENT er Array,” IEEE Transactions on Mi- cy parasitic oscillations, a 10 µF elec- The author would like to thank crowave Theory and Techniques, Vol. 46, Fujiang Lin for on-wafer measure- October 1998, pp. 1391–1398. trolytic capacitor was connected in parallel with the drain supply. The ments and device modeling as well as Andrey V. Grebennikov received his Dipl Ing parameters of the matching circuit el- for helpful discussions and support. degree from Moscow Technical University of The Serenade 7.5 simulator is a prod- Communication and Informatics in 1980 and ements and the length of the mi- 1991, respectively. In 1983, he joined the crostrip line in the drain supply cir- uct of Ansoft Corp., Pittsburgh, PA. s scientific research department of Moscow cuit were chosen according to the re- Technical University of Communication and sults of the CAD simulation for a Informatics as a research assistant. Since References October 1998, he has been working with the high-efficiency operating mode of the 1. D.M. Snider, “A Theoretical Analysis and Institute of Microelectronics, Singapore. power amplifier. Only small fine tun- Experimental Confirmation of the Opti- Grebennikov can be reached via e-mail at ing of the variable capacitors in the mally Loaded and Overdriven RF Power firstname.lastname@example.org.