VHDL Tools You need simulation & synthesis tools. They are normally separate. Note that VHDL may simulate OK but synthesise incorrectly, so normally both are required when testing VHDL hardware descriptions. Modelsim EEE computers or free download from State of the art compiler & Xilinx - use with Xilinx ISE Webpack simulator Synplify EEE computers State of the art synthesis Xilinx ISE Download free from Xilinx Synthesis to Xilinx FPGA Webpack For most purposes Xilinx tools are adequate, however Modelsim gives faster & more accurate simulation. This course assumes you are using departmental version of Modelsim & Synplify.