# SERA A Soft Error Rate Analysis Methodology by mps12334

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```									               SERA:
A Soft Error Rate Analysis
Methodology

Ming Zhang and Naresh Shanbhag
University of Illinois at Urbana-Champaign

November 7-11, 2004
Outline
 Background
 Soft error rate analysis (SERA) methodology

 Motivations.
 High-level probabilistic model for combinational

logic SER.
 SERA: a divide and conquer approach.

 Accuracy, efficiency, and examples.

   Conclusions
Soft Errors
Cosmic rays

Error
n
p+         p
1

0
n
n+           n+-
p         + +
-
- -+
+

   Other possible sources
   alpha particles
   neutron induced B10 fission
Outline
 Background
 Soft error rate analysis (SERA) methodology

 Motivations.
 High-level probabilistic model for combinational

logic SER.
 SERA: a divide and conquer approach.

 Accuracy, efficiency, and examples.

   Conclusions
Soft Errors in Combinational Logic

System

Architecture

Circuit Design                          SERA
Semiconductor Device Physics   n+ p n+-+ -+-
-+ +

Nuclear Physics
Outline
 Background
 Soft error rate analysis (SERA) methodology

 Motivations.
 High-level probabilistic model for combinational

logic SER.
 SERA: a divide and conquer approach.

 Accuracy, efficiency, and examples.

   Conclusions
Soft Error Rate (SER)

Number of errors
per unit time
SER  R    P(SE)
Particle hit rate (sec-1)

Effective particle hit
ratio

Probability of soft error
given an effective
particle hit

   Divide and Conquer!
Particle Hit Rate: R

- Ziegler, IBM J. R&D, 1996          R :- particle TRC,rate ( sec-1)
Baumann, hit 2000

F(E)
Emax
R          F ( E)  dE  Atotal
Emin

Atotal                              57 neutrons/m2 * sec
at NYC sea level
Effective Particle Hit: 

n+           n++      +
p        -      -
+ +-
- +
+

   Effective particle hit results in charge generation.
   An abstraction of a series of physical processes. Not the
main focus of this work.
    : effective particle hit ratio.
   Derived by comparing proposed SERA model with
Hazucha’s empirical SER model for SRAM.

  2.2 105    A technology-independent fitting parameter
Probability Space
   P(SE) : probability of soft error given an effective particle hit.
   Effective particle hit events:
 HC
(j) : Output of a combinational gate (including PI).

 HS
(i) : Sampling input of a D-flip-flop (or latch).

 HM
(i) : Storage (memory) element of a D-flip-flop (representing PO).

 HO : An irrelevant position.

Particle
hits
SET
HS(i)             HM(i)
D         Q

B           SET
D         Q
Q

D
CLR

SET
Q
HC(j)                                               Q
CLR

A
CLR
Q                                                   SET
D         Q
SET
D         Q
Q
HO
CLR

CLK           CLR
Q

Input DFFs                      Combinational                Output
circuit                    DFFs
Impact of Circuit Design Space on SER
HO
HM(i)
HS(i)
HC(j)
D-Latch   D-Latch
Path 1       D                             Q
.
.
.
Path Nj                CLK      CLKB
Master    Slave

 Fan-out                    Clock frequency
 Logic depth                Setup & hold time
 Logical masking            Latch design
 Gate size                  Supply voltage
 Supply voltage
Soft Error Probability P(SE)

SET
D         Q

B              SET
D         Q
CLR
Q
SET
D         Q
CLR
Q

A
CLR
Q                                                                      SET
D         Q
SET
D         Q
CLR
Q

CLK            CLR
Q

 The soft error probability at the ith primary output.
M
P ( SE )   P ( SE ( i ) HC ( j ) ) P ( HC ( j ) ) +P ( SE ( i ) HS ( i ) ) P ( HS ( i ) ) + P ( SE ( i ) HM ( i ) ) P ( HM ( i ) )
(i )

j 1

Combinational                       DFF sampling                           DFF memory
gates                                input                                element
Conditional Probability
P( SE (i ) HC ( j ) )                       f Q (q) fT (t0 )dt0 dq
( q ,t0 )S c j )
(

Soft error inducing
(q,t0) combinations
Probability density
function of charge q
Probability density
function of particle
hit instant t0
fQ(q)                          fT(t0)
Exponential                           Uniform

q                                  t0
Soft Error Probability P(SE)

Chip layout, e.g.                                           Ac( j )
P( HC )    ( j)

Atotal

M
P ( SE )   P ( SE ( i ) HC ( j ) ) P ( HC ( j ) ) +P ( SE ( i ) HS ( i ) ) P ( HS ( i ) ) + P ( SE ( i ) HM ( i ) ) P ( HM ( i ) )
(i )

j 1

 Circuit simulation
 Logic simulation
 Graph theory
Outline
 Background
 Soft error rate analysis (SERA) methodology

 Motivations.
 High-level probabilistic model for combinational

logic SER.
 SERA: a divide and conquer approach.

 Accuracy, efficiency, and examples.

   Conclusions
SERA: Divide and Conquer

Inverter Chain
Extractions                User Interface

Circuit                 Logic Simulation

•Circuit topology
Path Search          •Input vectors
•…
•Transistor size
•Supply voltage
•setup time
SER Analysis Engine
•…
•Probabilistic
model
SER for Combinational Logic Circuits
(either for a specific input vector or averaged)
Circuit Simulations on Inverter Chains
Particle hit                                         Particle hit
Particle hit
HC(j)                                               HM
HS
D-Latch   D-Latch

N+1       j+1           j       2        1
CLK      CLKB
Master    Slave

      0                , t  t0

I ( q ,t0 ) (t )   2q t  t0  t t0
  p
        
e            , t  t0

q : amount of colleted charge
t0 : instant of particle hit
- IBM J. R&D, 1996
 : technology-dependent time
constant
- Hazucha,   IEEE Trans. Nuc. Sci. 2000          Cosmic ray neutron
strike induced current
Conditional Probability vs. Clock Period
0.5
Conditional probabilities

0.4
DFF memory element
DFF sampling input
0.3               inverter 1 input
inverter 2 input
inverter 3 input
0.2               inverter 4 input
inverter 5 input

0.1

0
0   0.2   0.4          0.6   0.8     1
Tclk (ns)

   Please see full paper or backup slides for more examples.
   Emulate logical masking, for a
given input vector. Repeat such        j

process for a large number of
inputs.
   Cha, FTCS 93
   Path search algorithm gives a
conservative estimation of total
number of paths and
corresponding path lengths
between any given pair of          i
particle strike location and
primary output node.

t
SER Analysis
Em ax

SER(i )      F ( E )dE    A
Em in
d

 M N i , j ( Lk )                                                            
  P +P( SE (i ) HS (i ) ) P( HS (i ) ) + P( SE (i ) HM (i ) ) P( HM (i ) ) 
                                                                             
 j 1 k 1                                                                   
   SER(i): soft error rate of ith primary output depends on
   Neutron flux (spectrum)
   Effective particle hit ratio
   Drain area (circuit layout)
   Circuit topology
   Input vector
   Particle strike location (N or P-type drain) and logic state of the node
before strike. (Such terms are not explicitly shown in the above
Outline
 Background
 Soft error rate analysis (SERA) methodology

 Motivations.
 High-level probabilistic model for combinational

logic SER.
 SERA: a divide and conquer approach.

 Accuracy, efficiency, and examples.

   Conclusions
SER vs. Bit Position and Input Vector

Bit 1                         Bit 11

Bit 21                        Bit 32
16 x 16 multiplier
SER vs. Circuit Size

8x8                           32 x 32

Design implications: Protect the center bit(s).
B
SER bounds:     max SER   (i )
 SER   SER    (i )
i
i 1
SER Comparison: Multiplier and SRAM
Multiplier: SER vs. (Vdd, tset)

   Design Implications
   Insensitive to Vdd (good for low-power design)
   Strong function of setup time (bad for high speed design)
Validation of SERA Methodology
   SERA v.s. empirical        Random Number Generator      IN1
IN2

SER model for               Data set:
1) Input vector

SRAMs.                      2) Particle hit location
3) Current source
parameters( Polarity, q,
IN3
Node1

IN4
tPH )
   Good matching (diff.
< 8%) for various         HSPICE simualtion
IN5
Node2    Node3

process technologies
and supply voltages.    P(SE|HC): Probability
Node4
of soft error, given an

   SERA v.s. Monte             effective particle hit at
one of the candidate
circuit nodes (Node1 -
D
SET

Carlo SER                                                               Node5           Q
Node5)
Test Circuit              CLR
Q
OUT

simulations for
comb. ckt.
   Good matching
(diff.<4%).
   106 run time speed-
up!
Conclusions
   SERA methodology is systematic
   Works for both combinational logic and memory.
   Employs a judicious mix of probability theory, circuit
simulation and graph theory.
   Technology scalable
   Compatible with empirical models
   SERA is fast and accurate.
   Circuit simulations are only performed on extracted
inverter chain circuits.
   Captures dependence of SER on Tclk, Vdd, tset, thold, logic
depth, circuit topology and input vectors.
Backup
Conditional Probability vs. DFF Setup Time
0.5
Conditional probabilities

0.4
DFF memory element
DFF sampling input
inverter 1 input
0.3               inverter 2 input
inverter 3 input
inverter 4 input
0.2               inverter 5 input

0.1

0
60   80      100        120           140
tset (ps)
Conditional Probability vs. Supply Voltage

Conditional probabilities   0.5

0.4               DFF memory element
DFF sampling input
inverter 1 input
0.3               inverter 2 input
inverter 3 input
inverter 4 input
0.2               inverter 5 input

0.1

0
1.4   1.5     1.6        1.7
Vdd (V)

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