Group 12 An Efficient Flash Tran

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					  An Efficient Flash Translation
Layer Scheme for Flash Memory

                    Dongchul Park
                    park@cs.umn.edu
                     March 10, 2009


                                      1
                       Agenda
• Motivation
• Existing approaches
  – Sector-level mapping
  – Block-level mapping
  – Hybrid-mapping
     • BAST (Block Associative Sector Translation)
     • FAST (Fully Associative Sector Translation)
• Problem definition
• References
                                                     2
                   Motivation
• NAND Flash memory
  – Has become more common in many mobile devices.
  – Advantages
    • High speed, nonvolatile, reliable, less power, shock
      resistant.
    • Cost per bit has continuously decreased.
  – Block and page
    • Flash memory consists of lots of blocks.
    • Each block is composed of 32(or 64) pages.
    • Read/write in page unit, erase in block unit.

                                                             3
                     Motivation
• Characteristics of NAND Flash memory
  – Erase-before-Write
     • Overwrite is not allowed.
     • If overwrite is required, erase a block then write to the
       one of the pages within the block.
         Causes different READ/WRITE operation performance.
  – Limited # of write per cell
     • Flash memory cell has a limited life span for writing.
        – 10K for MLC, 100K for SLC.
         Wear-leveling is required.

                                                                   4
                  Motivation
• FTL (Flash Translation Layer)
  – To change the logical sector number of file system
    into physical sector number of flash memory




                                                         5
                          Motivation
• Issues in FTL (Flash Translation Layer)
   – Performance bottleneck
      • Flash memory suffers from the write bandwidth problem
            – Erase-before-write
      • Erase operation requires a very high cost.
            – 7~10X slower than Write operation.
            – 60~100X slower than Read operation.
   – Memory requirement
      • All address mapping tables are saved in SRAM in Flash memory.
      • SRAM is very fast, but very high cost.

   – Goal
      • To minimize the # of erase operation.
      • To minimize the memory usage.

                                                                        6
   Sector-based V.S. Block-based
• Sector-level mapping
  – Map LSN of file system to PSN of flash memory
     • Flexible: can select any one of all empty sectors in flash
       memory
     • Large space: save mapping table information of all
       sectors




                                                                    7
            Sector-based V.S. Block-based
    • Block-level mapping
         – Map LBN of file system to PBN of flash memory with
           LSO (Logical Sector Offset)
               • Small space: save mapping table of only block
               • Low block utilization, degradation of overall performance
                  Unnecessary merge operations




Let SN # of sector per block
LBN=LSN/SN
LSO=LSN%SN                                                              8
           Hybrid mapping (BAST)
• BAST (Block Associative Sector Translation)
   – Blocks are classified to two types
      • Data block: for data saving (block-level mapping)
      • Log block: for overwrite operations (sector-level mapping)
   – Once overwrite occurs
      • Empty log block is assigned and write the data to it.
   – Merge operation
      • If all log blocks are assigned
      • If all sectors of a log block are filled and overwrite occurs into the
        same log block
   – Problems
      • Low space utilization
          – Log block thrashing (ex. S0, S4, S8, S12, S0, S4, S8, S12)
          – Hot logical block (ex. S0, S2, S1, S3, S1, S0, S2, S3)

                                                                                 9
Hybrid mapping (BAST)




                        10
        Hybrid mapping (BAST)
• Log block thrashing




                                11
        Hybrid mapping (BAST)
• Hot logical block




                                12
         Hybrid mapping (FAST)
• FAST (Fully Associative Sector Translation)
  – Based on BAST scheme
  – Log block is classified into two types
     • Sequential write: overwrite occurs from first (#0) page
       within a block  SWITCH operation
     • Random write: not from first page  MERGE operation
  – Less merge operation and high space utilization
     • All data blocks share log block
        – Fully associative


                                                             13
Hybrid mapping (FAST)




                        14
         Hybrid mapping (FAST)
• Disadvantages
  – Low utilization of log block
     • If overwrite to the first page of each block is requested
       repeatedly  causes repeated merge operations of SW log
       blocks
  – High cost of merge operation
     • Merge operations of random write log block  each sector
       in RW log blocks needs merge operations to each data block
       which is associated to the RW log block.
         – Fully associative
  – Round robin victim selection
     • Choose one of the RW log blocks as victim in a round robin
       fashion

                                                                    15
            Problem definition
• Problem
  – Erase operation requires a high cost in flash
    memory performance.
  – Erase operation is closely related with merge
    operation in FTL scheme.

• Goal
  – To minimize the # of merge operation in FTL
    scheme so as to improve overwrite performance.
     • Improve overall flash memory performance.

                                                     16
                                    References
•   A reconfigurable FTL (flash translation layer) architecture for NAND flash-based applications,
    CHANIK PARK, WONMOON CHEON, JEONGUK KANG, KANGHO ROH, WONHEE CHO, and JIN-SOO
    KIM. ACM Transactions on Embedded Computing Systems (TECS), July 2008.
•   A log buffer-based flash translation layer using fully-associative sector translation, Sang-Won Lee,
    Dong-Joo Park, Tae-Sun Chung, Dong-Ho Lee, Sangwon Park, and Ha-Joo Song. ACM Transactions on
    Embedded Computing Systems (TECS), July 2007.
•   An adaptive two-level management for the flash translation layer in embedded systems, Chin-Hsien
    Wu and Tei-Wei Kuo. ICCAD, 2006.
•   An Efficient FTL Algorithm for Flash Memory, Tae-sun Chung and Hyung-Seok park, 2005
•   FAST: An Efficient Flash Translation Layer for Flash Memory, Sang-Won Lee, Won-Kyong Choi, and
    Dong-Joo Park, 2006.
•   A space-efficient flash translation layer for compactflash systems, Jesung Kim, JongMin Kim, SamH.
    Noh, SangLyul Min, and Yookun Cho, IEEE Transactions on Consumer Electronics,2002
•   System software for flash memory: a survey. CHUNG, T. S., PARK, D. J., PARK, S. W., LEE, D. H., LEE, S.
    W In Proceedings of the 2006 IFIP International Conference on Embedded And Ubiquitous
    Computing (EUC 2006). (Aug.) Seoul, Korea
•   LSTAFF: System Software for Large Block Flash Memory, Taesun Chung, et al, LNCS, 2005
•   Small-Block vs. Large-Block NAND Flash Devices, Techinical note TN-29-07, Micron Technologies.
•   A. Ban, "Flash File System," United States Patent, No. 5,404,485, April 1995




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