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Final Year Project 20062007 Final Year Project 2006 2007 Progress Report Student

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									          Final Year Project 2006/2007
                Progress Report



Student Name:         Alan Concannon



Student ID:           03853276



Course:               Electronic & Computer Engineering



Project Supervisor:   Dr. Fearghal Morgan



Project Title:        Implementation of an existing Spartan
                      3 FPGA application development
                      platform on to the Digilent Nexys FPGA
                      board to perform a range of DSP
                      functions.
                                                                                         2



                                                                         Abstract

The aim of this project is to produce further development of a previous years final
year project work. The existing project is a Spartan 3 FPGA based embedded system
that performs a range of DSP, image and data processing functions in real time. This
Project will perform these functions faster by taking advantage of the Digilent Nexys
on-board USB data transfer capabilities. This project, as with the previous years
project, will contain a GUI that displays a picture and allows a user to interact with
this picture. The user can then navigate the GUI to implement a number of functions
that will manipulate the image. The final product will be a very compact, user-
friendly project that will demonstrate the capabilities of the Digilent Nexys board.




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                                                                   Table Of Contents



ABSTRACT ..................................................................... 2
TABLE OF CONTENTS .................................................. 3
CHAPTER 1 INTRODUCTION .............................................. 4
1.0 PROJECT AIM........................................................................................... 4
1.1 METHODOLOGY ..................................................................................... 5
         1.1.1 HARDWARE ............................................................................. 5
         1.1.2 SOFTWARE .............................................................................. 7
         1.1.3 TOOLS ................................................................................... 10
CHAPTER 2 VHDL ................................................................ 11
CHAPTER 3 CELLULAR RAM ........................................... 12
CHAPTER 4 FUTURE WORK ............................................. 14
CHAPTER 2 CONCLUSION .....................................................
REFERENCES ...............................................................




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                                             Chapter 1 Introduction
_____________________________________________________________________


1.0 Project Aim
.
The main objective of this project is to further develop an existing Spartan 3 FPGA
(Field Programmable Gate Array) embedded system. The existing embedded system
uses a USB (Universal Series Bus) module to improve data transfer speeds, which
connects to the Spartan 3 board via an external connector. In this project the Digilent
Nexys board will be used which introduces on board USB capabilities and a more
robust and compact solution. This system will incorporate the following:
       Allow transmission and reception of image data to and from a PC via USB
       whilst saving this data to the on board PSRAM(Pseudo Static Random Access
        memory).
       Perform a range of image processing techniques using the Digilent Nexys
        board.
       Perform a range of DSP (Digital Signal Processing) techniques using the
        Digilent Nexys board. E.g passing the data through a digital FIR (Finite
        Impulse Filter) filter that is implemented using FPGA logic.
The completed project should provide a user-friendly and compact embedded system
which will allow the user to manipulate using a range of data processing techniques
This system may then be used in the future to demonstrate the capabilities of the
Digilent Nexys board and the overall ability of FPGAs to carry out high level task at a
minimum cost to the user.




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1.1 Methodology
1.1.1 Hardware

1.1.1.1 Digilent Nexys Board [1]

The Digilent Nexys circuit board is an integrated circuit development platform based
on the Xilinx Spartan 3 FPGA The Nexys board provides a number of useful I/O
devices and numerous ports that make it an ideal platform for experiments with FPGA
based digital systems. The Nexys board is suitable for a range of designs from low-
level logic circuits to high-level digital systems and is fully compatible with all
versions of the Xilinx ISE tools. The Nexys board includes the following features:


      A 200,000 gate Xilinx XC3S200 FPGA with 500+MHz operation (400,000
       and 1,000,000 gate versions are also available)
      USB2 port for FPGA configuration and high speed data transfers (using
       Digilent Adept Suite Software
      Multiple power configurations (USB, batteries or wall plug)
      16MB of fast Micron PSDRAM (Pseudo Static Dynamic Random Access
       Memory) and 4MB of Intel StrataFlash Flash ROM (Read Only Memory)
      50MHz Oscillator
      Xilinx Platform Flash ROM for long term storage of FPGA configurations
      Connector for VGA (Video Graphics Array) hi-resolution graphics LCD
       (Liquid Crystal Display) panel or 16x2 character LCD display.
      8 LEDS (Light Emitting Diodes), 4 seven segment displays, 4 pushbuttons and
       8 slide switches
      60 FPGA I/Os routed to on board expansion connectors
In this project many features of the Nexys board are used. The USB port is used for
FPGA configuration and data transfer to and from the host computer. The Micron
PSDRAM is used to store the data that will have the DSP functions performed on it.
Although there are three system clock settings on the Nexys, this project will use the
50Mhz clock.




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                             Figure 1 Digilent Nexys Board




                             Figure 2: Nexys Block Diagram




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1.1.2 Software

1.1.2.1 Digilent Adept Suite [2]

This software is used to provide a user with a platform to program the FPGA that is
situated on the Nexys system board. The Digilent Adept Suite (DAS) allows JTAG
(Joint Test Action Group) configuration of Xilinx logic devices that have Ethernet and
USB capabilities. The DAS consists of four pieces of software:

    Export
        This tool is used to program Xilinx FPGAs, PROMs and CPLDs by accessing
        the JTAG scan chain. Export supports two configuration file types .bit files
        and SVF (Serial Vector Format) that are both used to program JTAG devices.
        SVF files are used to program any JTAG devices whereas .bit files are used to
        program FPGA devices.
       Transport
        Transport allows communication and data transfer to take place with correctly
        configured FPGA devices. Before Transport can be used the FPGA must be
        configured to read and write data to specific registers. The user can stream
        data from a saved file to the FPGA or can store data to a file that has been
        streamed from an FPGA. Transport also allows the user to read or write
        individual bytes to and from an FPGA or to write multiple bytes to multiple
        registers simultaneously.
       Ethernet Administrator
        This software is used to configure the firmware of Ethernet Modules. Ethernet
        Administrator (EA) must be run before any of the previously mentioned Adept
        software tools can be used to access any module. Parameters such as Device
        ID, IP Address, subnet mask and Gateway Address must be set using EA prior
        to any data transfer or JTAG programming.
       USB Administrator
        Digilent USB Administrator (DUA) is used to configure the ID string
        contained in the firmware of a USB device. Each Digilent USB device has a
        specific ID string that the DUA displays once the device is connected. The
        Adept suite keeps track of communication modules in a list called the device


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       table. A device must be added to this list before any of the other Adept
       software tools can be used with it. The USB Administrator and Export are
       both used in this project.
1.1.2.2 Xilinx ISE (Integrated Software Environment)

The Xilinx Integrated Software Environment (ISE) is a software suite that allows a
user to take a design from the design entry stage through to the Xilinx device
programming stage. The ISE Project Navigator provides management and processing
of the design by implementing the following steps in the ISE design flow. design
through the following steps in the ISE design flow. This project uses the ISE project
navigator version 8.2i to implement the design.


     Design Entry

    This is the very first step in the ISE design process. During this stage the user
    creates the project source files based on the design objectives. Programming
    languages can be used to create the top-level design file i.e Hardware
    Description Languages(HDL) such as Verilog, ABEL or VHDL, alternatively, a
    schematic may be used. A number of formats may be used to create the lower
    level source files in the design. The designer may be working with a synthesized
    EDIF(Electronic data Interchange Format) file that has been generated by a third
    party design entry tool or an NGC/NGO file, if this is the case, design entry and
    synthesis can be skipped.


     Synthesis

    Once Design Entry has been completed the designer may run the synthesis tool.
    During this stage the language design used e.g. VHDL or Verilog is converted
    into netlist files that are used as inputs into the implementation process. Once this
    step is completed a synthesis report is generated which can be viewed. A
    Technology and Real-Time Logic(RTL) schematic is also created. The Syntax is
    checked and once verified, the next step may be implemented.




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     Implementation

    Once the implementation tool has been run the logical design is converted into a
    physical format(e.g. Bit File) that may be downloaded to the specified target
    device. In this project the target device is the Spartan Nexys board. From within
    Project Navigator the implementation process may be run in one or multiple steps
    depending on whether the designer is targeting a Field Programmable Gate Array
    (FPGA) or a Complex Programmable Logic Device (CPLD).Multiple reports are
    generated during this stage that may be useful to the designer.


     Verification

    Verification may be carried out at multiple stages in the design flow. Simulation
    software such as Modelsim can be used to test the timing and the functionality of
    the whole design or a particular part of the design. Simulation allows the designer
    to create and verify complex functions speedily. During simulation, the source
    code used e.g. VHDL or Verilog is interpreted into circuit functionality and
    logical results of the described HDL are displayed to determine the correct
    operation of the circuit.


     Device Configuration

    Once a programming file has been generated, the target device may be
    configured. A programming file generation report is also available after this stage
    is completed. During configuration, the Xilinx tool generates configuration files
    and programming files may be downloaded from a host computer to a Xilinx
    device.




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1.1.2.3 Modelsim: Xilinx Edition
Simulation software such as the Modelsim version provided as part of the Xilinx ISE
allows testing of a design prior to downloading it to a target device. Simulation may
be carried out at multiple stages of the design flow depending on the particular
designers taste. There is a better chance of detecting errors and bugs early in the
design if simulation is carried out sooner rather than later. This may save hours of
work in the future. During simulation a test bench is created which models the
external signals of the “Unit Under Test” and stimulus is then applied to these signals.
The designer may view a timing diagram of the overall process that shows the
response of all inputted and outputted signals. Simulation tools therefore can reduce
the design to production time if used correctly.


1.1.3 Tools
1.1.3.1 Very High-Speed Integrated Circuit (VHSIC) Hardware
Description Language
VHDL can be used to describe the concurrent and sequential behavior of a digital
system at many levels of abstraction ranging from the algorithmic level to the gate
level. VHDL is an IEEE standard. A VHDL file has a .vhd or .vhdl extension.
A system may be completely designed in software, tested and validated before it is
implemented in hardware. The design may be broken up into smaller parts and
described using a Hardware Description Language. VHDL is a technology
independent industry standard and is non-proprietary unlike schematic entry tools.
VHDL design entry is faster than schematic entry. Behavioural VHDL enables test
bench stimulus generation, complex bus functional model creation and file IO. The
VHDL design database provides formal design documentation.




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                                                        Chapter 2 VHDL
_____________________________________________________________________


So far in the project not much new VHDL code has been written but some parts of the
code have been edited. The foundation of this project is based on the appliedVHDL
course that was introduced by Dr. Fearghal Morgan. Every member of the 4th year
Electronic Engineering degree and the 4th year Electronic & Computer Engineering
degree has completed this module in the first semester as part of the Digital Systems
Design and VHDL course. The appliedVHDL course provided the following:
       UART - For communication with the Visual basic GUI which provides the
        user with an interface to carry out a Delta function
       displayCtrlr – Displays the data as it is being transferred from the host to the
        board and vice versa
       datCtrlr – Bundles and unbundles byte wide data into 32 bit word length
        and sends it to the UART
       dspBlk – Performs a delta function that subtracts one image from another.
       IOCSRBlk – Decodes UART control/data byte sequence, provides CSR
        read/write access, activates DSP task and activates datCtrlr module
       MemCtrlr – DSP and IO read/write access to memory
This appliedVHDL course demonstrated data, in the form of two bitmap images being
received and transmitted from the host system via the uart. The data is then saved to
the on-board SRAM and a DSP delta function carried out on both bitmap images.


The appliedUSBSimple project, FYP 05/06 by Shane Agnew provides a system that
allows FPGA configuration and high-speed data transfer via the Digilent USB2
module to the Spartan 3 board and also supports data transfer via the UART. This is
the system that this project attempts to transfer onto the Digilent Nexys board without
the UART capabilities.




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                                           Chapter 3 Cellular RAM
_____________________________________________________________________

The Digilent Nexys board used in this project contains a completely different memory
design to the Spartan 3 board in the appliedUSBSimple project that used the
ISSIIS61LV25616AL high speed SRAM organised as 256K * 16 bits. The Nexys
utilises the Micron MT45W8MW16BGX cellularRam that is a high-speed pseudo
RAM developed for low power, portable applications. This particular device has a
128Mb DRAM core organised as 8Mb*16 bits and includes a burst mode, which
increases read/write bandwidth. The functional block diagram below illustrates device
operation.




                         Figure 3. Functional Block Diagram


In order for the existing project to be transported onto the Nexys board, the cellular
RAM memory device must be described in VHDL and integrated into the project. The
cellular RAM will operate in Asynchronous Mode that uses the industry standard
SRAM control bus (CE#, OE#, WE#, LB#/UB#). READ operations are initiated by
bringing CE#, OE#, LB#/UB# low while keeping WE# high. Valid data will be driven
out of the I/Os after the specified access time has elapsed. WRITE operations occur



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when CE#, WE#, LB#/UB# are driven low. During asynchronous write operations,
the OE# level is a “Don’t Care”, and WE# will override OE#, the CLK input must be
held static LOW.




                             Figure 4. Read Operation




                             Figure 4. Read Operation




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                                            Chapter 4 Future Work
_____________________________________________________________________

Although I am finding it difficult at the moment to make progress hopefully I can
organize and manage the tasks at hand better. The Nexys board is giving trouble at
present. Windows XP is constantly looking for drivers and sometimes won’t
recognize the device at all. The tasks completed to date are as follows:
      Completion of the appliedVHDL 4th Year Semester 1 course.
      Review of Shane Agnew’s FYP
      Review of Antoin O’hAllmhurain’s FYP
      Implemented Part2 of AppliedVHDL course (cascadedBCDCntImpl) on the
       Nexys board to test functionality
      UCF file altered and ready to access CSRs on Nexys board but the board is
       now dysfunctional.


The goals for the immediate future are:
      Design the cellular RAM memory device in VHDL and implement project on
       the Nexys
      Review DSP fundamentals and Xilinx DSP course notes
      Implement an FIR filter in VHDL




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                                References

      [1] Digilent Nexys Board user guide
       http://www.digilentinc.com/Data/Products/Nexys


      [2] Digilent Adept User Manual
       http://www.digilentinc.com/Data/Products/Nets1_RM.pdf




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