ENGR 3420 Lab 4 March 29, 2005
CMOS Inverter Characteristics
In this lab, you will use the signal generator and the oscilloscope to measure various static
and dynamic characteristics of a CMOS inverter.
1. MOS Transistors in Series and Parallel. Consider the pair of matched nMOS transis-
tors, shown on the left in each part of Fig. 4.1. By calling these transistors matched,
we mean that their properties are identical (e.g., they have the same width, length,
threshold voltage, and threshold current, and they are operating at the same tempera-
ture), so that, if the same terminal voltages were applied to both devices, their channel
currents would be identical. For this question, we shall assume that the Early eﬀect is
negligible. Recall that we can express the channel current of an MOS transistor in a
source/drain symmetric form given by
I = Is (f(VGB , VSB ) − f(VGB , VDB )) , (1)
where Is is related to the channel current of the transistor at threshold and f(·) is a
function that assumes an exponential form in weak inversion and a quadratic one in
strong inversion. For an nMOS transistor, the bulk is connected to ground, so the
three potentials in the model would simply be VG , VD , and VS .
(a) Use the source/drain-symmetric model to show that two identical nMOS tran-
sistors with the same gate voltage connected in parallel, as shown in Fig. 4.1a,
behave as a single nMOS transistor with twice the channel current of either single
device for any combination of VG , VS , and VD .
(b) Use the source/drain-symmetric model to show that two identical nMOS transis-
tors with the same gate voltage connected in series, as shown in Fig. 4.1b, behave
as a single nMOS transistor whose channel current is half that of either single
device for any combination of VG , VS , and VD .
Hint: Assume the form given in Eq. 1 for the current ﬂowing through each device,
apply Kirchhoﬀ’s current law at the intermediate node, and try to eliminate the
intermediate node voltage from the equations. Note that you don’t need to know
the form of f(·) in order to accomplish this feat.
VD I VD
VG VG 2 VG 1/2
Figure 4.1: Two matched nMOS transistors connected with their channels connected in (a)
parallel and (b) series. The parallel connection behaves just as if it were a single nMOS tran-
sistor whose current is twice as large as either of the individual devices. The series connection
behaves as if it were a single nMOS transistor with half the current of either device. The
same is true for pMOS transistors.
4.3 Inverter Characteristics
The static characteristics of an inverter are usually described by a voltage transfer charac-
teristic (VTC), which is sometimes also called a DC transfer characteristic. The VTC is
essentially a plot of the inverter’s output voltage as a function of its input voltage. A typical
inverter VTC is shown in Fig. 4.2a. When the inverter’s input voltage is low, its output
voltage is high. When the inverter’s input voltage is high, it’s output voltage is low. For
each input voltage, we deﬁne an incremental voltage gain of the inverter as the slope of the
VTC at that point. The incremental voltage gain basically tells us by how much the output
voltage will change for a given small change in the input voltage at any point along the
curve. Note that the VTC has a negative slope everywhere, which implies that the inverter’s
output voltage decreases as its input voltage increases and vice versa. The VTC has three
distinct regions: two in which the curve is relatively ﬂat and one in which the curve is quite
steep. We normally operate the inverter in one of the two ﬂat parts of the curve when we use
it as a logic gate. By keeping the inverter biased in the steep part of the VTC, we can also
use it to linearly amplify small signals. The logic high (VIH ) and low (VIL ) threshold voltages
are deﬁned by where the slope of the VTC is negative one. Input voltages below VIL are
considered to be logical 0s and input voltages above VIH are considered to be logical 1s. The
range of input voltages between VIL and VIH is called the transition region. The point in the
transition region where the inverter’s input voltage is equal to its output voltage is called the
transition threshold (VM ). The incremental gain of the inverter attains its maximum value at
the transition threshold, so we would like to operate the inverter at or near this point when
using it as an ampliﬁer.
The dynamic characteristics of an inverter are usually quantiﬁed both in terms of prop-
agation delays (tpLH and tpHL ) and in terms of a rise time (tr ) and a fall time (tf ). Typical
input and output waveforms for an inverter are shown in Fig. 4.2b along with deﬁnitions of
= -1 50%
= -AV Vout
dVin Vdd tpHL tpLH
VIH VMVIL Vdd Vin tf tr
Figure 4.2: Various inverter characteristics. (a) Static voltage transfer characteristic (VTC)
of an inverter with deﬁnitions of the transition threshold (VM ) and the logic high (VIH ) and
low (VIL ) threshold values. (b) Dynamic characteristics of an inverter with deﬁnitions of
propagation delays from high-to-low (tpHL ) and low-to-high (tpLH ), rise time (tr ), and fall
time (tf ).
the propagation delays and the rise and fall times. The propagation delays express by how
much time a logic transition is delayed when it goes through the inverter. Propagation de-
lays are normally measured between the 50% points on the input and output waveforms, as
shown in Fig. 4.2b. Note that, in general, the propagation delay for a high-to-low transition
is diﬀerent from the propagation delay for a low-to-high transition. The rise and fall times
of an inverter express how much time each type of transition takes to occur. These times
are usually measured between the 10% and 90% points of the output voltage waveforms, al-
though sometimes they are speciﬁed as the time it takes for the output voltage to transistion
from VIL to VIH or vice versa.
4.4 General Facts about CMOS Chips
In this lab, you will be working with a complementary metal-oxide-semiconductor (CMOS)
chip, which is packaged in a DIP package. CMOS chips are generally very sensitive to
electrostatic discharge (ESD), which you have probably experienced ﬁrst-hand by dragging
your feet across a carpet in the winter and getting a shock when you touch a light switch
or another person. This section provides some basic guidelines for safe handling of CMOS
Figure 4.3: Electrostatic discharge (ESD) protection circuitry.
4.4.1 Handling CMOS Chips: Preventing Electrostatic Discharge
CMOS chips are extremely prone to damage by static electricity. The breakdown ﬁeld of an
insulator is the electric ﬁeld above which the atoms that constitute it ionize, permitting a
direct path for electrons to ﬂow through it. For example, when lightning strikes, so much of
a potential diﬀerence has built up between the clouds and the earth, that the electric ﬁeld
exceeds the break-down ﬁeld of air, the air molecules ionize, and there is a direct current
path between the clouds and the earth (i.e., the lightning bolt). Recall that the current
ﬂowing through the channel of an MOS transistor is controlled by an insulated gate. The
layer of silicon dioxide (SiO2 ) between the gate electrode and the silicon substrate is very
thin—for the chip that you will be using in this lab, the gate oxide is probably between 30
and 50 nm (i.e., 30 × 10−9 m and 50 × 10−9 m) thick. Even a few tens of volts dropped across
such a short distance amounts to a huge electric ﬁeld in the SiO2 , approaching its breakdown
ﬁeld of about 109 V/m, causing the gate oxides to blow out. During a short walk across the
lab, you can easily build up a few kilovolts (i.e., a few thousands of volts) of static electricity
on your body. If you touch the pins of the chip, you can easily blow out the delicate gate
There are typically some ESD protection structures on CMOS chips, such as that shown
in Fig. 4.3, comprising diode clamps to the power-supply rails. Normally, the voltages that
we apply to the pins on the chip fall between the two power supplies (i.e., ground and VDD ).
If we try to take the voltage on a pin with ESD protection, one or more of these diodes
will forward bias, and take the current that we are supplying to move the voltage on the
pin outside of the power rails. If we were to zap the chip with some static electricity, these
diodes would eat some of it, but more often than not, these ESD protection structures are
often just not enough to save the gate oxides from getting popped. There are some very
simple precautions that you can take so your chips will survive from one lab to the next:
1. When the chip is not powered up in the breadboard, keep it stuck into a black piece of
conductive foam or in the IC tube. The conductive foam keeps all of the pins nearly
shorted together, preventing substantial voltage diﬀerence between the pins. The IC
tube prevents you from touching the chips altogether.
2. Always discharge yourself to chassis ground before picking up or touching a chip.
For instance, you could discharge yourself by touching the snap in the corner of the
grounded mat on top of your lab bench. Any charge that has built up on you will then
go to ground instead of into your chip. Between discharging yourself and picking up
the chip, don’t move your feet.
3. Always try to handle chips by their plastic package, not by the pins.
4.4.2 Powering Up the Chip
Before inserting a chip into the breadboard, you should hook up all of the power and ground
connections to all of the correct pin locations. You will need to hook up VDD and ground, even
if you are testing an isolated transistor, because the static protection structures on the gate
inputs need to be powered and the n-wells (i.e., the substrate in which the pMOS transistors
live on the chip) need to be biased correctly.
Then, hook up the rest of the circuit. Next, turn on the power supply and adjust the
voltage to whatever value is needed (VDD should be +5 V for the chips that you will be
testing), and turn the current limit down until the voltage just begins to drop and the red
LED labeled CC turns on. Then turn the current limit up a little bit. This procedure will
keep excessive current from ﬂowing into your chip in the event that you have hooked up
something incorrectly (e.g., you have hooked +5 V where you should have put ground and
Next, turn oﬀ the power supply, disable any other voltage sources that you have hooked
up, such as the signal generator, and then insert the chip into the breadboard carefully.
You can then turn power back on and enable the other voltage sources. If the voltage from
the power supply drops suddenly, it probably means that you have hooked up something
incorrectly and the power supply is current limiting. The chips that you will be testing
should only draw a few milliamps.
You will be doing two experiments in this lab. In Experiment 1, you will use the signal
generator and the oscilloscope in XY mode to examine the VTC of a CMOS inverter. In
Experiment 2, you will examine the dynamic characteristics of the inverter. The chip that
you will be using is called the CD4007 dual complementary pair plus inverter, which contains
three nMOS transistors and three pMOS transistors that are reasonably well matched in a
14-pin DIP package. A pinout of the CD4007 is shown in Fig. 4.4. You can use any of the
transistors on the chip, but you must connect pin 7 to ground and pin 14 to VDD so that the
ESD protection circuitry and n-wells are biased properly.
4.5.1 Experiment 1: Static CMOS Inverter Characteristics
From an nMOS transistor and a pMOS transistor on a CD4007 chip, make a CMOS inverter
in your breadboard. You can use any of the three pairs of transistors on the chip, but
regardless of the pair that you choose, don’t forget to connect pin 7 to the ground rail and
Figure 4.4: Pinout of the CD4007 dual complementary pair plus inverter chip.
pin 14 to the VDD rail, so that the substrate and well are properly biased. Use the signal
generator to supply a triangle wave that goes between ground and VDD to Vin. Connect the
input and output of the inverter to the two channels of the oscilloscope. Put the scope in XY
mode and adjust the channel 1 and channel 2 oﬀsets, the vertical gains, and the timebase
to display the inverter’s VTC on the scope. When you have the scope settings in a nice
place, you might consider turning on averaging to get a nice clean curve. Obtain a plot of
the VTC for your lab report. Determine VIL , VIH , and VM for your inverter. Also, determine
the inverter’s incremental voltage gain at the transistion threshold. Label your plot of the
VTC with these features.
Change the eﬀective size of either your nMOS transistor, or your pMOS transistor, or
both by adding one or both of the unused transistor on your CD4007 chip in series or in
parallel with those that you used to make your original inverter. What eﬀect does this
change have on the inverter’s VTC? Obtain a plot of the new VTC for your lab report and
determine the same parameters as you did for the original inverter.
4.5.2 Experiment 2: Dynamic CMOS Inverter Characteristics
Now, use the signal generator to supply a square wave to your original inverter and take
the scope out of XY mode. Obtain scope traces for your lab report showing the high-to-
low transistion and the low-to-high transisiton that your inveter makes. Use the scope to
determine tpLH , tpHL , tr , and tf for your inverter. Annotate your plots with these parameters.
Repeat this experiment for the same altered inverter that you used in Experiment 1.
VIL VM VIH Vdd Vin
Figure 4.5: VTC of an unreliable inverter circuit.
The general shape of the VTC of the inverter is critical to the reliable operation of digital
circuits. Because the magnitude of slope of the VTC is less than unity on the ends of the
VTC (i.e., in the logic high and low parts of the curve) and it is larger than unity in the
transition region, the inverter has two very important properties that make digital circuits
robust. The ﬁrst is called noise immunity and the second is called signal restoration or signal
regeneration. These two properties are surely related to each other, but not identical.
Noise in electronic circuits is any undesired (and very often unpredictable) ﬂuctuation in
the value of a signal, such as the input or output voltage of an inverter. Some noise results
from the random thermal motion of charge carriers within the devices that make up the
circuit, and so is fundamentally unavoidable. Other noise results from coupling between the
circuit and the rest of the world, and so can often be reduced by proper shielding. By saying
that the inverter has noise immunity, we mean that its output voltage does not respond to
noise in its input signal.
By saying that the inverter can restore or regenerate a digital signal, we mean that if
an input signal is not quite above the threshold for a logical 1 or below the threshold for
a logical 0, the inverter’s output will be closer to a valid logic level than was the input.
After only a few stages of inversion, the signal will be restored or regenerated to a legitimate
value. In essence, an inverter can take a weak 0 and turn it into a strong 1 or it can take
a weak 1 and turn it into a strong 0. We simply could not build digital circuits with many
stages of processing if it weren’t for this restoring property. If the signals are not restored
in some fashion, then, after many stages of processing, oﬀsets due to device mismatch and
noise would accumulate such that the system outputs have nothing whatever to do with
the system inputs. Instead, they would be determined by noise or by some mismatch in
the components making up the system. Noise immunity and signal restoration are the real
strengths of digital systems over analog ones. Moreover, they are the reasons that we can
build digital computational systems of enormous complexity.
Explain how the general shape of the VTC shown in Fig. 4.2a results in the inverter having
the properties of noise immunity and signal restoration. Also, explain why an inverter circuit
with a VTC such as the one shown in Fig. 4.5 would not possess these properties and why
it would be useless in building reliable digital systems.