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CMS Tracker FED - Front End FPGA DCI version IO by asafwewe

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CMS Tracker FED - Front End FPGA DCI version IO

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									                                  CMS Tracker FED - Front End FPGA
                                           DCI version I/O
                           Clock 40      3                           Clock40
                                                                     Reset


                        delay_ser_out    3
                        delay_ser_in     3                           Frame_Sync_out
                                                                     Frame_Sync_In             Frame_Sync
                         busy            3

                         adc enables    12                           Readout_Sync_out
              ‘DC’                                                   Readout_Sync_In  Readout_Sync
                           Opto Rx      6
              ‘DC’                                                   Monitor_Sync_out
                                                                     Monitor_Sync_In           Monitor_Sync & Serial_Load
                                                Front End
                                                  FPGA               Full Flags

                ADC_Data_stream_0        10

                                                                  8 Data_stream                80 Mhz

                ADC_Data_stream_11       10                                                             Design I/O Total = 162



                       Configuration                                     JTAG

                      Bank Voltages                                     TEMP SENSE
                                                                                                         XC2V1000FG456 - 324 I/O
                                                                        Bank DCI Resistors
                       Core Voltage                                                                      XC2V1500FG676 - 396 I/O

Rutherford Appleton Laboratory   Instrumentation Department   Electronic System Design Group    Rob Halsall et al.    16 January 2002
                                    CMS Tracker FED - Front End FPGA
                                          DDR/DCI version I/O
                             Clock 40       3                          Clock40
                                                                       Reset


                           delay_ser_out    3
                           delay_ser_in     3                          FS_RS_out
                                                                                                      Frame_Sync & Readout_Sync




                                                                                            80 MHz
                            busy            3                          FS_RS_In
                                                                       MO_SD_out
                            adc enables    12                          MO_SD_In                       Monitor & Serial_Data
              ‘DC’
                             Opto Rx       6
              ‘DC’

                                                  Front End
                                                    FPGA
                       ADC_Data_stream_0 5




                                                                                            160 MHz
              80 MHz




                                                                    4 Data_stream

                       ADC_Data_stream_11 5                                                                     Design I/O Total = 100



                          Configuration                                  BSCAN
                                                                                                                 XC2V1000FG456 - 324 I/O
                          Bank Voltages                                   TEMP SENSE                             XC2V1500FG676 - 396 I/O
                                                                          Bank DCI Resistors                     XC2V2000FG676 - 456 I/O
                         Core Voltage
                                                                                                                 XC2V3000FG676 - 484 I/O
Rutherford Appleton Laboratory     Instrumentation Department   Electronic System Design Group          Rob Halsall et al.    16 January 2002
                                       CMS Tracker FED - Front End FPGA
                                                  Floorplan
                                 Die                                                                  Package




                       Channel 0
        ADC_Data




                                                             FE-BE I/O
                                                   Control



                        Channel 11


                      Delay - Opto - ADC
                                                                                               Same frame 456 & 676 ?


                                                                                             XC2V1000FG456 - 324 I/O
                            Clocks                                                           XC2V1500FG676 - 396 I/O
                                                                                             XC2V2000FG676 - 456 I/O
                                                                                             XC2V3000FG676 - 484 I/O


Rutherford Appleton Laboratory         Instrumentation Department        Electronic System Design Group   Rob Halsall et al.   16 January 2002
                                                                            CMS Tracker FED
                                                                   Synch & Processing FPGA
                   Synch & Processing FPGA
             per adc channel phase                                                                                                                                            1x
          compensation required to bring                                                                                                                                                           Clock 40




                                                                                                                                                                                    DLL
                                                                                                                                                                              2x
                 data into step
                                                                                                                                                                              4x                   MHz

                                                                                                                                                                                                   Synch in




                                                                                                                                                                                    Synch
                                                                        2 x 256 cycles         256 cycles                                           nx256x16                                       Synch out




                                                                                                     Hit finding
                                                trig1             trig2                trig3                       trig4                                                                           emulator in
                    Registers




                                                                            Re-order
                                                        Ped sub




                                                                                                                               Sequencer-mux
                                                                            cm sub
                                                                                                                                                                                                   Synch error
                                       sync




                                                                                                                                                         DPM
              10                10               10                11                   11                         8 s-data                    16                  16
                    Phase




  ADC 1                                                                                                            8 s-addr
                                                                                                                                                     d         d                                   Global reset




                                                                                                                                                                                    Control
                                                                                                                    hit                        8                   8                               Sub resets
                                                                                                                                                     a         a
                                                                                                                    No hits                                                                        Full flags

                                                        header              status                                         8
                                                                                                          averages




                                                                                                                                                                        mux
                                                                                                                                                                                                    control




                                                                                                                                                                                    Packetiser
                      4x




                                                                                                                                                                                                  8 data
ADC 12                                                                    256 cycles           256 cycles                                           nx256x16




                                                                                                   Hit finding
                                                trig1             trig2                trig3
                    Registers




                                                                                                                               Sequencer-mux
                                                                            Re-order
                                                        Ped sub




                                                                            cm sub
                                       sync
                     Phase




                                                                                                                                                         DPM
              10                10               10                11                   11                         8 s-data                    16                  16
                                                                                                                                                     d         d




                                                                                                                                                                                    Serial Int
                                                                                                                   8 s-addr                                                                       Serial I/O
                                                                                                                   hit                         8                   8
                                                                                                                                                     a         a
                                                                                                                    No hits

                                                        header             status                                          8
    Opto Rx                                                                                               averages
                    Local
                     IO




    Opto Rx

    Delay Line
                                                                                                                                                                                                   B’Scan
                                                                                                                                                                                                   Config


Rutherford Appleton Laboratory                Instrumentation Department                       Electronic System Design Group                                  Rob Halsall et al.                16 January 2002

								
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