Analog Design Considerations for Deep Submicron CMOS Processes

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					     Analog Design Considerations for Deep Submicron CMOS Processes
                                   James S. B. Mason
             IBM UK Laboratories, Winchester, England jsbmason@uk.ibm.com


        ABSTRACT
In deep submicron processes there are an increasing number of technology issues affecting device
performance and reliability. Some are familiar from earlier technologies, such as electromigration, and
are increasing in severity with decreasing feature size. However others, such as diffusion proximity
and gate leakage, are now becoming significant issues at the circuit level. The implications of some of
these effects for analog design are covered within this paper.


        INTRODUCTION

 During conventional circuit design, devices are normally considered as independent entities whose
characteristics are determined from the device equations and modelled for a simulation tool. However
the performance of individual devices may be significantly affected by other devices or structures
within close proximity. Moreover device characteristics are becoming increasingly complex with
reducing feature size introducing further issues to be considered within the circuit design phase such
as leakage currents or departure from classical device behaviour. Finally, technology limitations such
as electromigration and hot carrier effects can modify circuit performance significantly during the
lifetime of the system.


1.      Stress Effects ( Isolation Proximity )
 The mobilities of carriers in silicon are affected by mechanical stress, in strained silicon technologies
( 1 ) this is used to improve transistor switching speeds. In the case of electrons the mobility is reduced
in both transverse and longitudinal compression. For holes, the mobility is reduced with compression
in one direction and increased when the strain is in the other direction. Since there is a compressive
strain force associated with the oxide isolation boundary, the effect of the isolation boundary is to
increase PFET currents and decrease NFET currents.

 This effect can have significant implications for maintaining device matching in analog circuits,
especially with multi-fingered devices where the edge devices are affected by the isolation edge.
Consider the simple FET layout of Figure 1(a), the single FET device is subjected to stress on both
sides due to the proximity of the oxide isolation, also known as shallow trench isolation ( STI ), at the
edge of the source/drain diffusions. By inserting dummy devices as shown in Figure 1(b) , the
isolation edge is moved away from the active finger and so this reduces the device stress and therefore
characteristic mismatch from the ideal. It is also possible to move the isolation edge away from the
active device and not include the dummy devices although, for other reasons, maintaining device
symmetry by including these extra devices is good practice.

 The isolation proximity effect has significant implications for many circuits. In some cases because of
symmetry it may not be immediately apparent, for example in source coupled pairs, where the input
FETs are layed out identically and so subject to the same stress effect. This may be beneficial in
applications where speed is important whereas in other circuits where tracking and offset matter it may
not. In circuits where ratioing is important, it can be a significant problem and the layout of such




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circuits needs to be carefully managed. It is possible to accurately analyse this effect in extracted
netlists where the isolation to gate distance is known for each device and can be used to modify the
device model if it is below a certain threshold.




Figure 1(a) and 1(b): The effects of isolation stress on FET devices



 Consider the current matching between two FETs, one with the isolation edge an infinite distance
away from the gate edge ( along its width ) and the other with one of the edges brought in towards the
gate. Using device models for an 80nm technology the mismatch curve of Figure 2 was obtained. This
shows that the mismatch in currents can reach 15% due to this effect, in a device where both isolation
edges are close to the gate it will reach 30% and such a mismatch has been observed in hardware.




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Figure 2: Mismatch in current for a device subject to isolation proximity stress effect compared to an
unaffected device. The affected device has the isolation edge on one side of the gate out at infinity and
on the other edge at a distance shown on the x axis. The separate curves are for differing widths and
lengths for the FETs ( given in um ).



2.      Diffusion Proximity

 As processing geometries reduce, secondary effects in ion implantation can significant affect the
performance of devices as dopant atoms are scattered from adjacent photoresist. An example of this is
the influence of well edges, for example N well, on the threshold voltages ( Vt ) of FET devices placed
close to the well edge. As shown in Figure 3, devices which are close to the N well edge ( typically
less than 1um in a deep submicron process ) will receive additional dopants which will modify the
channel implant. Consequently, these devices will have a different threshold voltage to other devices
which are situated further away from the well edge and therefore not subject to this scattering effect.

 This effect can be modelled and compensated for in device simulation with the Vt of the device
increasing as the well edge approaches the device. The Vt offset can reach tens of millivolts in
magnitude and this can have a significant affect on analog circuit performance. Again standard analog
precision layout techniques relying on symmetry and identical placements can help alleviate this
problem, as can increasing the separation between analog devices which need to be matched and well
edges. Clearly the process limits on separation defined in the design ground rules may not be sufficient
for good device matching.




Figure 3: Ion implant dopant scattering at N well photoresist into neighbouring P well



3.      Ion Implantation



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 Ion implantation, which is used to create device diffusions, can create device asymmetries resulting in
matching issues. Ion implantation can be performed at an angle to the silicon surface rather than
perpendicular to it and this can result in device asymmetry due to the directional nature of the implant
and imbalances when the device is subject to multiple implants from different directions. An example
of where this effect can occur is the channel implant on FET devices used to control the FET threshold
voltage. The implant is arranged as multiple angled implants into the source and drain regions as
shown in Figure 4. Since the source and drain are subjected to two different implants, which cannot be
identical, the device will not be truly symmetric.

 The asymmetries introduced by ion implantation are not normally modelled and so need to be
mitigated on critical devices within the layout by maintaining orientation across matched devices.
Another alternative would be to use techniques such as rotational symmetry where devices are split
into parallel sub-devices placed at different orientations to each other. The overall composite device
could them be arranged so that it would not see any imbalance due to ion implantation




Figure 4: FET channel ion implantation and device asymmetry




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3.      Device Leakage

 In deep submicron CMOS technologies, the gate insulator thickness has reduced to 2nm and below on
high performance FETs, this translates to the width of ten silicon atoms. At such thicknesses,
tunnelling currents through the gate are becoming significant. In deep submicron technologies, several
gate thicknesses are often available. On a 90nm process, the gate leakage with a 1.4nm device may be
around 50 nA/um2 whereas for a 2.5nm device it is effectively zero. In analog circuits where gate
leakage is important, for example sample and hold circuits or low current circuits, it may be possible
to simply substitute thicker FET devices. Of course a penalty is incurred with lower performance in
terms of transconductance and speed but this may well be acceptable in such circuits. Alternatively,
the gate leakage can be compensated for with additional circuitry, for example using other devices to
track and balance the leakage. Fortunately, this tunnelling current can be accurately modelled and
therefore detected at the circuit design stage.

 At the chip level, the increased leakage currents can be a serious issue for static power consumption
and IDDQ testing and this is well documented in the literature. The gate dielectric forms the basis of
most on-chip capacitance devices with the thinner gates obviously providing the greatest capacitance
per unit area. The leakage current of such capacitors can approach 0.5A/cm2 and this highlights the
problem of static current on large chips. The use of such capacitors in analog circuits in such critical
areas as phase locked loop filters requires careful consideration of the leakage.


4.      Hot Carrier Effects
 Reducing device geometries and the associated increase in electric field strengths within devices
results in higher carrier velocities. These so-called hot carriers can damage the gate-oxide interface,
degrading the device performance, and can also tunnel into the gate itself becoming trapped charge
and adding to the threshold voltage offset on these devices. There is also the possibility of substrate
hot carriers where carriers are thermally generated from the depletion regions of reverse biased
junctions, these carriers can also be injected into the gate oxide regions of devices.

 Hot carrier effects have been an issue with earlier technology generations where the problem was
considered to be more of a reliability or failure issue. However, the hot carrier effect is now a more
pervasive issue whereby high performance circuits undergo degradation during the lifetime of the
chip. This needs to be considered at the design phase, the device degradation is not constant but is
dependant upon the duty of the specific device.



5.      Negative-Bias Thermal Instability ( NBTI )
Negative-Bias Thermal Instability is a particular problem for p channel FETs which can exhibit an
increase in trapped positive charge during symmetrical Vds stress causing an increase in threshold
voltage over time. Either negative voltages or high temperature can cause NBTI and an accelerated
shift occurs when both conditions are concurrent. Interestingly NBTI is not a new problem, it was first
reported in 1967, but the stress conditions are now more commonly found during normal operation
with deep submicron designs.




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 The design of pFET circuits can be seriously affected by NBTI as for a matched pair of devices, a
systematic offset in the threshold voltages will result if the gate biases are unequal. Additionally,
NBTI can also introduce mismatch shifts across the chip and random mismatches between devices.

  The impact of both HCE and NBTI can be assessed within simulation by applying biases on devices
according to their duty, thereby reflecting the individual effects of these stress mechanisms over the
chip lifetime. An example of this is shown in Figure 5, which shows the transient performance of a
voltage controlled oscillator as designed and after test, burn in and operation over the specified
lifetime of the part. The latter simulation was performed with modifications to the individual models
within the circuit netlist to represent the effect on the individual devices of the test and lifetime stress
in terms of shift in parameters such as threshold voltage and gate matching. As can be observed, in this
circuit the stress results in a reduction in the oscillation frequency of the circuit.




Figure 5: VCO performance: Output ( V ) vs Time ( ns) before and after degradation defined as test
and burn-in stress followed by 170k hours of operation at max supply voltage and 100degC ( 9.7E17
stress cycles )



6.      Electromigration
Electromigration is an electrochemical effect by which metal ions from the interconnect are attracted
towards the positive anode,. This flow of positive ions is induced by the electron flow and is
somewhat analogous to the flow of sediment in a river. The consequence is that electromigration
results in the depletion and accumulation of material with voids on the cathode side of the wire and
hillocks at the anode side. Eventually a void will result in failure of the line as the effective width
reduces and the current density in the remaining wire increases to a fusing level. Similarly hillocks can
result in a short circuit with adjacent metal lines. The photomicrograph shown in Figure 6 is of an
electromigration failure at an interlevel metal via on a modern CMOS process, this is an example of a
void failure where the wire has failed as an open circuit.




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 The problem of electromigration is not new and has been an issue with integrated circuit design for
many years. However with reducing geometry size, the current levels at which electromigration limits
are reached now approach levels that may be found in individual circuit nets rather than in power
busses and the other high power wiring where it has traditionally been an issue. In a modern 100nm
copper based CMOS technology, the electromigration current limit for a minimum size wire is around
100uA for 100k power on hours at 100C. Analog circuits may be using operating with currents in the
10uA to 1mA range and so are subject to this limit. Moreover since such circuits typically have nets
operating at dc, they can be particularly susceptible to this problem.

 During the design of analog circuits, the electromigration limits should be considered and for circuit
nets where the limit is approached or exceeded, a property can be attached to the wire at the schematic
which can be used during layout and verification to ensure appropriate wire widths are implemented.
The use of redundancy techniques can also be useful in this situation, for example using a cluster of
vias rather than individual vias for intermetal connections and the same with contact areas from wires
onto the devices themselves.




Figure 6: An example of electromigration failure at an interlevel via



7.      Self Heating Effects
Somewhat akin to electromigration is self heating and this may limit the design of some components,
especially polysilicon resistors. Conventional devices are contained within the bulk silicon which
provides a reasonable thermal sink. Modern processes typically offer polysilicon resistors which are
made by blocking the salicide step on the selected polysilicon shapes defining the resistor. These
resistors offer good performance including low self capacitance since they are not situated within the
bulk but this does mean that the power handling is reduced. Typically, the current is limited to less
than 1mA per micron width of resistor, the effect of the self heating is normally to increase the resistor
value over time. Again this problem is best handled at the circuit design level by annotating currents
on circuit nets so that they can be checked during layout and verification. Some circuit simulators also
allow power limits to be set for a component which can then raise an alert if the value is exceeded
during a simulation testcase.




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Design and Verification Strategies

In ensuring that circuit performance is maintained during layout and placement onto a chip, the circuit
design and layout process needs to be more tightly connected. The circuit designer has a good
understanding of how circuit operation may be affected by parametric shifts but does not always know
how layout decisions may affect individual devices. The layout designer knows how individual
devices are arranged and has an understanding of how the layout should be arranged for best wiring
and signal flow but probably does not have a detailed understanding of circuit operation. Apart from
improving the communication between these two operations, the conventional solution to this problem
is post layout circuit extraction and resimulation. However this step is not totally rigorous in that the
coverage of this simulation tends to be significantly less than that originally performed and so
problems may not actually be found. As the system is assembled, this problem is compounded as the
complexity increases and the difficulty in identifying individual mismatches increases. The probability
of introducing such problems can also increase as circuits are placed adjacent to other structures which
may introduce new mismatches.

The following are some design practices that can be used to alleviate these problems:
   • Annotating circuit currents and matching requirements more thoroughly on circuit
        schematics, not only can these be an aid to layout but they can also be used for verification
   • Processing post layout circuit extraction netlists to identify critical devices, the individual
        model references can then be examined to check whether they have been modified due to
        layout or nearby structures, assuming that this is supported by the extraction tool. This can
        allow a quicker and more comprehensive identification of potential problem areas.
   • Schematic circuit currents can then be transferred to layout as shape properties. These can
        then be used with shapes processing tools to ensure electromigration and self heating limits
        on wires and devices are satisfied.
   • Using shapes checking tools to identify spacings around critical circuits which, although
        compliant with the technology processing ground rules, may cause a problem with device
        matching and performance.
   • If chip area restrictions permit, ‘guard band’ critical circuits, use any available area and do
        not limit layout to the minimum spacings defined by the process ground rules.
   • Device models can be ‘biased’ to account for long term shifts in parameters and simulations
        rerun with the modified models. In this way, it may be possible to desensitise circuits to such
        effects at the design stage.
   • Setting voltage limits for gate voltages within simulation, thereby allowing individual devices
        to be identified which exceed this limit during simulation testcases. This can allow devices
        that are susceptible to gate voltage overstress or NBTI to be more readily identified.



        CONCLUSIONS

  In deep submicron circuits, interactions between devices and with other structures nearby have
become a serious issue in maintaining circuit performance. The reduction in component geometries
towards the atomic scale is increasing the significance of non-ideal effects on device performance.
This is causing problems both with the initial design and in maintaining performance over the chip
lifetime. Technology limitations, such as electromigration and static power, which have previously
been considered as reliability and testability issues at the chip level, are now becoming significant
considerations at the circuit level. These issues are complicating the design process and increasing the
risk in the development of system on chip solutions.
.




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        REFERENCES
(1) IBM's Strained Silicon Breakthrough Image Page
http://www.research.ibm.com/resources/press/strainedsilicon/

(2) The Electronic Structure At The Atomic Scale Of Ultrathin Gate Oxides
D. A. Muller, T. Sorsch, S. Moccio, F. H.Baumann, K. Evans-Lutterodt & G. Timp
Nature 399, 758-761 ( 24 June 1999 )

(3) Negative bias temperature instability: Road to cross in deep submicron silicon semiconductor
manufacturing
D. Schroder, J. A. Babcock
Journal of Applied Physics, Vol 94 No 1 ( 1 July 2003 )



       ACKNOWLEDGEMENTS

I would like to acknowledge the assistance of my colleagues at IBM, namely Matt Cordrey Gale,
Michael Sorna and Steven Zier, who have provided information used in this paper.




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Description: Analog Design Considerations for Deep Submicron CMOS Processes