VIEWS: 55 PAGES: 6 POSTED ON: 3/7/2010
A 245 GHZ LOW COST, HIGH PERFORMANCE VCO
TECHNICAL FEATURE AVE JOU OW R RN MIC AL REVIEWED D ED IT R OR A IAL B O A 2.45 GHZ LOW COST, HIGH PERFORMANCE VCO This article addresses performance and cost issues associated with voltage-controlled oscillator design. Although the example design is application specific, the methods demonstrated apply to microwave oscillator design in general. CAE and on-the-bench techniques are used for a comprehensive approach to the designing of microwave oscillators. E ngineers are under constant pressure to band phase noise can be considered using this reduce the cost of microwave designs equation: without sacrificing their performance. At 100 K volumes, oscillators can be produced 2 1 F at a fraction of the cost when compared to PM ( ) dBc / Hz = 10 log 2 2Qfm + 1 that of small-quantity purchased oscillators. This article presents a design procedure along with a practical example. An attempt is made C NkT 2kTR v K 2 • + 1 • + v to clarify some of the concerns associated with fm P fm 2 low cost, high performance microwave oscilla- tor design. Performance considerations in- where clude low phase noise, linear monotonic tun- ing, low harmonic emissions and adequate k = Boltzmann’s constant output power. T = temperature in Kelvin F = frequency of oscillation INITIAL TOPOLOGY SELECTION fm = offset frequency All oscillator circuits require a gain block Q = loaded Q and a feedback method. The topology used P = RF power at amplifier input here is based on the Barkhausen criteria for N = noise factor oscillation. Figure 1 shows that the design re- C = flicker noise corner frequency quires a network to provide the gain, a fre- Rv = tuning diode noise resistance quency selection network (resonator) and Kv = tuning gain (MHz/V) Fig. 1 A basic oscillator enough phase lag so that the overall phase for (The equation has been modified to include the configuration. w the loop is equal to 2π radians. A small-signal effects of varactor tuning.) Practical reduction scattering parameter approach of the oscillator’s noise sidebands is addressed GAIN is used to evaluate the design. BLOCK by increasing the loaded Q and signal-to-noise This method enables the use of LAG ratio (SNR) and decreasing both the flicker NETWORK a network analyzer for the and varactor modulation noise contributions. bench evaluation. Before proceeding with the RESONATOR design, Lesson’s equation for single-sideband phase noise JIM CARLINI 1 PM is examined. The various Detection Systems factors concerning single-side- Fairport, NY TECHNICAL FEATURE P1 P2 P3 4 shows the circuits used in the simula- tion. As the ESR of the capacitors used in the tank increases, the overall Q of the tank will decrease. As the tank’s un- loaded Q is reduced, its 3 dB band- width increases. This characteristic is 2.558 pF 1.65 nH 1.279 pF 3.3 nH 0.64 pF 6.6 nH shown in Figure 5 using single-port Z parameters. The 0.707 point of the Z parameter’s magnitude response repre- sents the tank circuit’s 3 dB bandwidth. Note how the band edges move out in v Fig. 2 Three 2.45 GHz tank circuits used in the simulation. frequency as the capacitor’s ESR in- creases from 0.2 to 0.8 Ω. 2.558 pF tank circuit produces a 1.65 nH 2.558 pF TANK rapid change in the reflection phase on RESONATOR DECOUPLING 3.30 nH 1.279 pF TANK either side of the resonant frequency, 6.60 nH 0.640 pF TANK The resonator is now evaluated as a making it the best L/C combination for two-port network. Decoupling ele- 150 the proposed resonator. ments are used to improve the res- A novel design approach was taken REFLECTION PHASE (°) 100 onator’s loaded Q. This configuration that uses a Coilcraft microspring air- provides valuable insight concerning 50 core coil. (This coil is available at great- the design of the intended oscillator. ly reduced cost when compared to that 0 One method used to study the loaded of a typical distributed ceramic or −50 Q for a two-port network is to evaluate Teflon resonator.) It was estimated that the rate of change in the phase slope, −100 the 1.65 nH coil could maintain a Q of which can be expressed as dφ/dω or at least 180 at 2.5 GHz. This Q value −150 group delay GD. The group delay dif- 1.0 1.5 2.0 2.5 3.0 3.5 was determined to be high enough for ferentiation process eliminates the lin- FREQUENCY (GHz) the intended resonator design. The air- ear portion of the phase response and core inductor is a primary component v Fig. 3 Simulation results for the three in lower frequency RF oscillator de- transforms the deviations from linear tank circuits. phase into deviations from constant signs. The problem at microwave fre- RESONATOR DESIGN group delay. It can be shown that the quencies is that the inductor Q de- loaded Q is related to the group delay The unloaded Q of the resonator ul- grades with frequency, particularly as by Qloaded = πfoGD. Group delay is the timately limits the oscillator’s loaded Q. the coil approaches its self-resonant rate of change in the phase of the for- The relationship between the loaded Q frequency (SRF). The SRF for the 1.65 ward transmission coefficient vs. fre- and noise sidebands can be written as nH inductor is greater than 10 GHz, quency. The nice thing about using –10log(Q loaded ) 2 . This relationship thus eliminating this concern. group delay as a figure of merit in res- holds true until the ratio of the loaded Care must be used in the selection onator design is that it can be evaluated Q to unloaded Q exceeds 2/3. To of the tank circuit’s capacitive element. with a simulator such as Microwave achieve a high unloaded Q the design As the capacitor’s reactance is reduced, Harmonica and also measured on the must maintain the lowest possible se- its potential to reduce the unloaded Q bench with a network analyzer. Note ries resistance and achieve the lowest of the intrinsic tank resonator is in- that the end coupling capacitors used possible L/C ratio for the components creased. A new line of high Q RF ca- increase the capacitive loading on the used in the tank. A fast change in the pacitors made by American Technical tank resonator. This effect requires the reflection phase on either side of the Ceramics was investigated. It was de- capacitor(s) in the tank circuit to be resonant frequency indicates a high termined that these RF capacitors dis- unloaded Q. Figure 2 shows three played an equivalent series resistance ESR = 0.2 Ω 2.45 GHz tanks used in the simulation. (ESR) similar to that of most mi- ESR = 0.5 Ω The simulation results shown in Fig- crowave capacitors at 2.5 GHz but with ESR = 0.8 Ω ure 3 clearly indicate that the 1.65 nH a substantial reduction in cost. Figure 4 Z MAGNITUDE (kΩ) P1 P2 P3 3 3 dB BW 2 1 3 dB BW 2.558 pF 1.65 nH 2.558 pF 1.65 nH 2.558 pF 1.65 nH 3 dB BW 0.2 Ω 0.5 Ω 0.8 Ω 0 2.30 2.35 2.40 2.45 2.50 2.55 FREQUENCY (GHz) v Fig. 5 Effects of the capacitor’s ESR v Fig. 4 Tank circuits used for the Z-magnitude simulation. on the tank circuit’s Q. TECHNICAL FEATURE P1 P3 It was decided to use the simple biasing network shown previously to reduce circuit complexity and cost. A 0.2 pF 0.4 pF DC bias current of approximately 10 2.0709 pF 1.72989 pF mA was used to determine a balance 1.65 nH 1.65 nH for the various noise-related bias con- cerns. In addition, S-parameter data 0.2 pF 0.4 pF with 10 mA bias are available from the manufacturer for the entire 6X6 family of transistors. P2 P4 v Fig. 6 The decoupled resonators. SUBSTRATE CONSIDERATIONS Since the design frequency is 2.45 tweaked in order to re-center the res- gain at the desired frequency. A resis- GHz, the PCB material is a significant onator’s center frequency. tor in the DC biasing network also consideration. In this application it is To examine the trade-offs concern- can be used for the prevention of considered preferable that the utilized ing insertion loss and loaded Q, a spurious moding. This goal is accom- swept display of several decoupled plished using a 51 Ω resistor. Figure 0.2 pF DECOUPLING resonators is shown. Different degrees 8 shows the intended gain block. 0.4 pF DECOUPLING of decoupling were used, as shown in The required biasing current has a 5 Figure 6. The 1.65 nH inductor is strong effect on the oscillator’s close- held constant while the tank’s capaci- in noise performance. As the bias 4 GROUP DELAY (ns) tor is adjusted to center the frequency current is increased, the close-in at 2.5 GHz. The simulation results phase noise that results from the de- 3 shown in Figure 7 clearly display the vice transposing low frequency base- increase in both group delay and in- band noise is degraded. This low fre- 2 sertion loss as the amount of decou- quency AM and PM noise is convert- pling is increased. The degree of de- ed into frequency fluctuations at the 1 coupling used in the final oscillator is a carrier by a nonlinear mixing process. trade-off between the goals of ade- This type of noise is referred to as 1/f 0 2.0 2.2 2.4 2.6 2.8 3.0 quate start-up gain and maintaining noise. In addition, as the bias current FREQUENCY (GHz) (a) the resonator’s loaded Q. is increased the device’s noise figure also increases, further degrading the 0 GAIN BLOCK DESIGN oscillator’s noise performance. This Often a discrete transistor can pro- result is due to a decrease in the os- INSERTION LOSS (dB) vide a much more cost-effective solu- cillator’s SNR. Contrasting the goals −2 tion than a MMIC. Although a little of minimizing the transistor’s bias more work is involved in designing an current to reduce noise is the fact oscillator using a discrete solution, it that the signal portion of the oscilla- −4 is well worth it if low cost is a primary tor’s SNR is improved with increased design concern. It is also advisable bias current. This effect occurs be- (although not necessary) to use a de- cause the absolute value for the noise −6 2.44 2.46 2.48 2.50 2.52 2.54 2.56 vice that presents a reasonable de- sidebands does not vary with the sig- FREQUENCY (GHz) gree of match at the intended fre- nal level produced by the oscillator. It (b) quency of oscillation. The device’s has been noted that both noise figure close match helps to ease the oscilla- and low frequency 1/f noise (flicker v Fig. 7 Decoupled resonator performance; (a) group delay and tor’s gain requirements. noise) are not affected significantly (b) insertion loss. A network that can provide for by an increase in the bias voltage. good spurious suppression should After evaluating cost and perfor- +5 V DC surround the transistor and usually mance for various families of transis- 150 Ω 100 pF produces unconditional stability at tors, an NE6X6-type device was cho- low RF frequencies. At lower fre- sen. These transistors are reasonably 51 Ω quencies, simple resistor biasing can priced, and data from the manufac- 3.9 pF 22 kΩ be used to accomplish this goal. As turer show that the NE6X6 devices 20 Ω the frequency increases, it is advis- have both low noise figure and low MICROSTRIP able to use choke biasing networks in 1/f noise characteristics. The transis- INDUCTORS order to avoid degrading the gain of tor’s VCEO (collector to emitter break- OUT the transistor any more than need be. down voltage with the base held IN ICE ≈ 10 mA A useful method for preventing mod- open) is 6 V DC. With V CE set to ing is to use resistive loading at out- 3 V, there is ample margin for peak- of-band frequencies. This configura- to-peak variations in the steady-state tion is used so as not to degrade the signal. v Fig. 8 The gain block’s schematic. TECHNICAL FEATURE material be very inexpensive and pro- produced in order to enable a two- noise performance.) The goals for the vide a well-controlled dielectric con- port analysis technique to be used. It initial simulation stage of the oscilla- stant. This characteristic is required is best to make the break at a point in tor design have been achieved. because the printed portion of the cir- the circuit where a reasonable degree cuit is used to control the amount of of match exists. The goal is to adjust TUNING CONSIDERATIONS phase lag between the transistor and the decoupling capacitors C2 and C3 Tuning of the oscillator’s center resonator. Since the printed portion of to allow enough gain for the start-up frequency is accomplished by using a the circuit exhibits only a relatively condition while minimizing the degra- varactor tuning diode. Since the cost minimal effect on the resonator’s dation to the loaded Q. The desired of the components becomes a critical loaded Q and loop gain, the attenua- gain margin for the open loop in this concern the tolerance used is often tion resulting from the substrate’s di- design is between 3 and 4 dB. A mini- not as tight as that of more extensive electric losses was not considered over- mum of 3 dB is suggested for ade- components. As an example, a 0.2 pF ly critical. After evaluating several op- quate start-up gain. The 4 dB maxi- capacitor nearly doubles in price as tions, including various sources of FR4 mum is recommended to prevent the the component tolerance is increased material, it was decided to use a low transistor from hard limiting any more from ±0.1 to ±0.05 pF. It is advisable cost material available from GIL Tech- than necessary. As the transistor is dri- to allow for deviation in the center nologies with a dielectric constant of ven harder into limiting, it will tend to frequency as a result of component 3.86 ±0.08. In addition, the substrate increase the production of undesired variations when evaluating tuning op- material is available for approximately harmonics. Reducing the loop gain tions. This design is intended for use the same price as FR4. also helps reduce the change in the in security sensor applications and is transmission phase during the oscilla- required to tune from 2.435 to 2.465 THE FINAL CONFIGURATION tor’s transition from small-signal to GHz. The oscillator’s tuning band- Having chosen the topology, a lin- large-signal conditions. width must extend far enough on ei- ear simulation was performed. This It is critical for the transmission ther side of these band edges to ac- procedure allows for precise adjust- phase to be 0° at the peak of the res- count for all of the component toler- ments in the phase for the intended onator magnitude response. It has ance variations. This concern must be design. A 2 pF capacitor located at been shown that degradation in the juggled with the fact that the tuning the collector is used to couple the sig- resulting noise sidebands due to diode’s noise contribution is magni- nal to the 50 Ω load. The initial nonoptimal transmission phase is re- fied as its tuning gain is increased. schematic for the oscillator is shown lated by 40log(cos θ).8 The microstrip The tuning gain is simply df/dV. The in Figure 9. A break in the circuit is transmission lines are used to adjust tuning diode is decoupled to reduce transmission phase. its tuning gain by using a capacitive After simulating the series combination in the resonator NE696M01 2 pF intended oscillator tank circuit. One of these capacitors BIAS design with various is the tuning diode. 3 V, 10 mA transistors from the The tuning diode’s effect on the TRL 50 Ω NE6X6 family it oscillator’s phase noise performance 0.3 Ω was determined can vary greatly depending on the C2 PORT 2 0.1 pF that the model type of tuning diode used, its tuning 0.3 Ω Q = 220 PORT 1 NE696M01 device gain and its Q. The modulation noise 1.65 nH 2.26 pF AT 2.5 GHz would produce the produced by the tuning diode is 0.3 Ω required start-up summed with the noise sidebands of C3 0.2 pF gain. The ft for the the oscillator and can degrade the os- NE696M01 transis- cillator’s phase noise performance. tor is 14 GHz with a Much of this noise is due to the mod- 3 V, 10 mA bias. ulation of the tuning diode junction v Fig. 9 The initial oscillator schematic. This ft is somewhat capacitance by baseband noise. Re- higher than desired for a 2.45 GHz ducing the baseband biasing resis- oscillator and is typical of the type of tance helps to reduce varactor modu- 5 150 6 trade-offs involved in oscillator de- lation noise. In this design the varac- sign. The simulation of the intended tor biasing resistor is only 200 Ω. In S21 MAGNITUDE (dB) GROUP DELAY (ns) 100 5 0 oscillation is shown in Figure 10. A addition, using a varactor with a less S21 PHASE (°) 50 4 50 Ω, 0.61 λ length of microstrip is abrupt tuning curve reduces the tun- −5 0 3 used to bring the transmission phase ing diode’s nonlinearity. However, as −50 2 to 0° at 2.45 GHz. The gain response the tuning curve becomes less −10 is peaked at 2.45 GHz. A gain of 2.63 abrupt, tuning linearity may be sacri- −100 1 dB is a bit low but considered enough ficed. Furthermore, the tuning −15 −150 0 2.2 2.3 2.4 2.5 2.6 2.7 for start-up concerns. The simulator diode’s series resistance degrades the FREQUENCY (GHz) shows that the group delay is 4.67 ns. oscillator’s loaded Q. It is suggested The loaded Q for the small-signal that samples of various tuning diodes simulation is approximately 36. (This be evaluated on the test bench prior v Fig. 10 The open-loop simulation. Q value shows the potential for low to final selection. TECHNICAL FEATURE 100 pF 100 Ω −20 +5 V PHASE NOISE (dBc) 0.1 µF 51 Ω −40 MICROSTRIP CHOKE 22 k Ω −60 20 Ω −80 −Vtune 3.9 pF MICROSTRIP −100 CHOKE 1 nF 200 Ω NE696M01 −50 0 50 2 pF FREQUENCY OFFSET (kHz) 50 Ω 27 nH 0.3 nH LOAD v Fig. 14 The oscillator’s phase noise 0.1 pF at 2.45 GHz in a 1 kHz RBW with 20 dB input attenuation. 0.3 Ω 0.8 pF 2 1.65 nH 0 Q = 200 0.3 Ω 0.3 nH −20 AMPLITUDE (dB) 0.3 nH 0.2 pF −40 1 0.3 Ω −60 0.7 pH 2.7 pF −80 1.0 Ω −100 0 2.6 5.2 7.8 10.4 13.0 FREQUENCY (GHz) v Fig. 11 The final schematic. v Fig. 15 The oscillator’s harmonics. INPUT RETURN INSERTION 0 Fig. 16 The oscillator’s output frequency vs. LOSS (dB) 10 LOSS (dB) 0 −5 tuning voltage. w −10 −10 −15 −20 −20 2.54 FREQUENCY (GHz) 2.21 2.45 2.69 2.21 2.45 2.69 2.50 FREQUENCY (GHz) FREQUENCY (GHz) 2.46 (a) (a) 2.42 OUTPUT RETURN 4 DELAY (ns) 0 2.38 GROUP 3 LOSS (dB) −3 2 −6 2.34 1 −9 0 1 2 3 4 5 6 7 8 9 10 0 −12 TUNING VOLTAGE (V) 2.21 2.45 2.69 2.21 2.45 2.69 (b) FREQUENCY (GHz) FREQUENCY (GHz) and justifies the resonator selection. (b) After evaluation of the oscillator v Fig. 12 The oscillator’s (a) insertion loss v Fig. 13 The oscillator’s (a) input with the network analyzer, the closed- and (b) group delay. and (b) output return losses. loop analysis is performed and the THE FINAL PROTOTYPE minimum by varying the VNA’s complete circuit is assembled. The The final schematic is shown in smoothing aperture. In this way the output power and phase noise were Figure 11. The rest of the microstrip best possible display of group delay is measured. Figure 14 shows the has been added, and provisions for obtained. A display of the oscillator phase noise to be –95 dBc at 10 kHz the tuning diode have been made. group delay and insertion loss is offset using a 1 kHz resolution band- The phase has been tweaked to adjust shown in Figure 12. The magnitude width. This noise level is considered for various distributed discontinuities of both transmission responses is more than adequate for most com- and parasitic reactances. Low induc- peaked at the intended frequency of munication receiver applications. The tance microwave grounding is main- oscillation. The input and output re- output power is 5.2 dBm at 2.45 tained by using 31-mil-diameter vias turn loss of the resonator is shown in GHz, which is a respectable signal to decouple all lumped components. Figure 13. The low reflections mea- level. The resulting RF-to-DC effi- Having established a promising sured at the resonant frequency vali- ciency is greater than nine percent. design with the simulator, the proto- date the VNA analysis technique. The VCO’s harmonics are shown in type VCO was constructed. An HP Having analyzed the group delay, the Figure 15. It is apparent by the fact 8720B vector network analyzer actual loaded Q is determined to be that the second harmonic is down by (VNA) was used to evaluate the open- 26. This value is 25 percent lower approximately 20 dB that the emis- loop oscillator. The number of test than the original simulated value and sion’s performance is quite satisfacto- frequency points determines the min- is attributed to slightly tighter cou- ry. By varying the tuning voltage be- imum resolution when recording pling in the actual circuit. However, a tween 3.3 and 5.9 V the frequency group delay data on the VNA. This loaded Q of 26 is considered re- changed linearly from 2.41 to 2.49 resolution is then increased from spectable for such a low cost design GHz. Figure 16 shows the output TECHNICAL FEATURE frequency vs. applied tuning voltage. optimization was to the tuning diode 3. George Vendilin, Anthony M. Pavio and Across this tuning span the output used. A practical microwave oscillator Uldrich L. Rohde, Microwave Circuit De- sign Using Linear and Nonlinear Tech- power varied by only 1.3 dB and vari- design has been demonstrated. niques, John Wiley and Sons, 1990. ations in phase noise were measured 4. Application Note AN1026, 1/f Noise Char- to be less than 2 dB. Tuning was ac- ACKNOWLEDGMENT acteristics Influencing Phase Noise, Cali- complished using a low cost Thanks go to Walter Budziak and fornia Eastern Labs. 5. Vector Measurements of High Frequency SMV1234-079 tuning diode from Al- Steve Carlini for help in reviewing Networks, Hewlett-Packard, April 1989. pha Industries. A second oscillator this article, and to Jayanti Venkatara- 6. Jeremy K.A. Everard, “Low Noise Oscilla- was built and tested in order to verify man at the Rochester Institute of tors,” IEEE Transactions on Microwave The- the design. (The test results were Technology for the use of the mi- ory and Techniques, 1992, pp. 1077–1080. nearly identical.) Using typical high crowave laboratory. Thanks also go to 7. M.J. Underhill, “The Need for Better Var- actor Diodes in Low Phase Noise Tunable volume pricing this circuit was built Jerry Hiller of Alpha Industries, Rick Oscillators,” IEE Colloquium, December for less than $1.30. Cory of M/A-COM and Olivier 1998, pp. 5/1–5/6. Bernard of California Eastern Labs CONCLUSION for discussions concerning the various Jim Carlini has been in the field of RF A design technique for using a microwave semiconductor noise electronics since 1980 commercially available simulator (Mi- mechanisms, and to Bill Dipoala for and is currently an RF crowave Harmonica) to evaluate low encouraging new product develop- design engineer at cost options for a 2.45 GHz oscillator ment at Detection Systems. s Detection Systems. He spent many years has been demonstrated. The design working on microwave was later analyzed on the bench using receivers for the a VNA and spectrum analyzer and References: government and was shown to display low phase noise, 1. D.B. Leeson, “A Simple Model of Feed- defense electronics linear tuning and low harmonic emis- back Oscillator Noise Spectrum,” Proceed- industry, and now ing of the IEEE, Vol. 54, February 1966, designs wireless UHF data links as well as S- sions. The output power was verified pp. 329–330. and X-band microwave sensor products for to be more than adequate for many 2. Randall W. Rhea, Oscillator Design and security applications. One of his main applications. The only on-the-bench Computer Simulation, Mcgraw Hill, 1995. responsibilities is the investigation of low cost design solutions. Carlini’s primary interest is in microwave electronics.
Pages to are hidden for
"A 245 GHZ LOW COST, HIGH PERFORMANCE VCO"Please download to view full document