Simulation and Modelling of Digital Delay Locked Loops
Rui L. Aguiar, Dinis M. Santos
Dep. de Electrónica e Telecomunicações, Universidade de Aveiro, 3810 Aveiro, Portugal
E-Mail: firstname.lastname@example.org, email@example.com
Abstract - This paper discusses some results for simulation and II. DLL MODELING
modeling of charge-pump Delay Locked Loops. A novel model
based on a sampled-time approach is presented, and used for A. DLL Delay Model
jitter analysis. The model is applied to input signal jitter,
internally generated jitter and is further extended to handle Our modeling is oriented towards DLLs with CP phase
jitter effects related with the control charge-pump. Behavior detectors, due to its increasing usage in clock-related
models for simulation purposes are derived from the theoretical applications. Fig. 1 presents a model for a DLL . A phase
model, and design considerations based on these are presented. a detector (PD) using a charge-pump circuit controls a voltage
controlled delay line (VCDL); this phase detector measures
I. INTRODUCTION the phase difference between input and output signals of the
Recently, delay locked loops (DLLs) have been VCDL. For most applications, the input signal is a clock
increasingly used in many applications. For instance, DLL waveform.
usage has been reported in clock distribution circuits [1,2], The following relations can be derived from simple
multiphase clock generation  and clock recovery circuits inspection of the model, when the DLL is synchronized:
. In all these applications, jitter analysis is of paramount
importance for good designs, and DLLs were used as they Φ out ( t ) = Φ in ( t − αT ) − K VCDLV (t ) (1)
introduce small jitter in signals and are easy to implement in c
digital circuits. In particular, DLL designs with charge-pump
Φ in ( t ) − Φ out ( t ) t
∫ I c (t )dt
(CP) phase detectors (PD) have shown to originate systems Vc (t ) = (2)
with good characteristics. Thus charge-pumped DLLs have C −∞
become increasingly used as elementary blocks in clock
related circuits. where α (1) is the total delay (in number of clock periods)
of the VCDL, VC(t) is the control voltage applied to the
Current DLL models [5,6] are based on more traditional VCDL, KVCDL is the VCDL gain (dΦout/dVC)1, and Ic(t) is the
PLL analysis. They do not provide design insight for DLL current applied to the capacitor C in the control node.
design or DLL jitter mechanisms, as they are either
extrapolations on PLL behavior or, at most, represent The PD will create short impulses (Up or Down )
practical knowledge about DLL performance. As DLL usage depending on the phase difference between Φin and Φout. As
increases and covers increasingly stringent conditions, these these are digital signals, their difference will be either 0, or
models present their limitations. CMOS applications ±1, and this will change the charge-pump state.
requiring high clock frequencies led to the on-going work in
DLL modeling here described. A discrete-time model for Ideally, when the DLL is near lock, the PD impulses will
charge-pump DLLs is presented in Section II. This model is
applied to jitter analysis, and overcomes the shortcomings of
previous approaches, as the line delay and the phase detector Φ in
are now considered. This analytic model is used to derive VCDL
behavioral models for DLL simulation, presented in Section
III. The paper presents simulation results supporting these +
proposed models, and explores these in order to achieve some Charge Vc
DLL design guidelines. Finally, conclusions are presented in PD Pump C
Section IV. -
Fig. 1. Charge-Pump DLL model.
This work has been sponsored partially by Portuguese programme Praxis In our expressions we assumed that as the control voltage increases, the
XXI, through the Genclock project. VCDL delay will decrease.
have a quasi-regular periodicity. A sampled time model [7,9] In Fig. 2, Θin is the input clock jitter, Θ∆T is the jitter
can approximate this behavior, where time impulses are generated in each DLL delay element, ηVc is the control
modeled by a quantitative value per (periodic) sample. We voltage noise; and Θout is the DLL output jitter.
will assume that the PD will only work on one of the clock
edges, and use this period as sampling rate. As the control Different TFs can be derived for each jitter source ,
voltage should only change during the time when the PD using the approximation strategy already described:
input waves are out-of-phase, we can also approximate VC by Θ ( z ) z −α − K T z −1 1 − K z α −1
its sampled value. J in ( z ) = out = = α T α −1 , (4)
Θ in ( z ) 1 − K T z −1 z − KT z
Thus, and applying the discrete Z-transform to this discrete for the input jitter TF;
model, we obtain the phase transfer function (TF): Θ ( z) KT (1 − z −α ) , (5)
JVCDL ( z ) = out =
Φ out ( z ) z −α − K T z −1 1 − K T z α −1 ΘVCDL ( z ) (1 − z −1 )(1 − KT z −1 )
H ( z) = = = α (3) for the jitter internally generated by the delay elements; and
Φ in ( z ) 1 − K T z −1 z − K T z α −1 Θ ( z)
JVC ( z ) = out = KVCDL , (6)
where the loop gain KT is given by KVCDL * KCP, with KCP the ΘVC ( z )
charge-pump phase detector gain. Note that KCP is much for the jitter generated by noise in the control voltage.
smaller than 1 in typical integrated circuits for clock related
functions. Total expressions for r.m.s. output jitter can be derived
from these jitter TFs, under the jitter premises above,
This expression readily shows the effect of total line delay: assuming gaussian noise . Thus, assuming gaussian jitter,
larger number of poles in origin (representing the larger and low values of KT, we achieve, from (4) and (5):
delay) and zeros will appear in the phase TF.
2π σδ 2π 1 + KT
(K ) ( )
B. DLL Jitter Models σin = α
− 1 + KT 1 − KTα ≈
2 2 2
1 − KT
T (1 − KT )
There are three main sources for output jitter in a DLL:
2π σε 2π (8)
1) jitter in the input clock, which is becoming important for σ VCDL = ≈ σ
clock distribution applications, as several distribution T (1 − K ) 2
methods are using interconnections of DLLs [1,2].
2) jitter generated internally in the VCDL, caused by noise in where σδ is the input signal jitter, σε is the internally
each delay element, or induced in those elements by power generated jitter, and σin and σVCDL are the output jitters
supply noise; originating by each case, respectively. (The output jitter for
3) jitter generated by noise present on the control voltage VC; the control voltage jitter is obvious from (6).)
this noise will change the total VCDL delay, and thus will This model is able to provide better insight into internal
translate as jitter at the output of the VCDL. DLL behavior, as the equations above incorporate both
Both phase detector induced problems (such as those control and delay effects into DLL performance, and are able
caused by noise in the phase detector circuitry or the to differentiate different jitter sources and effects. For
problems that may appear due to clock duty-cycle) and instance, a traditional statement is "a DLL is inherently
charge-pump inaccuracies can be modeled in our stable". This is the result of minimizing the importance of the
approximation as noise injected in the control voltage. control loop in DLL performance. From (3), the stability
Jitter behavior can be analyzed with the simplified model condition for charge-pump DLLs can easily be derived:
depicted in Fig. 2, where these jitter sources are modeled as KT < 1. (Note that stability does not depend on total line
additive stochastic processes inserted in the DLL model delay, but only on the loop characteristics.) In fact, typical
previously described. DLL designs are quite far from this limit value: KT values
smaller than 10-5 are common (e.g., [3,5]). Under this
condition, the results achieved with this model can be shown
+ to be similar to those previously presented in the literature
, leading to jitter accumulation factors approximately equal
to one. Both (4), (7) and (5), (8) lead to this conclusion. Note
that, for instance, if (7) shows that a DLL has a jitter
+ accumulation factor of approximately one for low values of
Θ in Charge Vc
PD + KT, it also provides more information. This expression also
Pump shows the overall behavior of input originated jitter
Θ ∆T -
mechanisms in a DLL: there is a component related with the
= immediate effect input jitter causes in the DLL control, and
+ another component related with the propagation of this
Φ out+Θ out
jittered signal across the VCDL, and their respective
relationships are dependent on the loop gain and total line
Fig. 2. Charge-Pump DLL jitter model
Operator OR 1
OR Logical Operator1
AND 0 .6
Memory 0 .2
Fig. 3. Matlab model for the Müller C-element. 0
40 60 80 100 120
Fig. 5. Output clock jitter, for normalized control voltage noise of 0.08,
in an eye-diagram representation.
Output clock jitter in functions of normalized control voltage noise.
Noise 0.02 0.05 0.08 0.1 0.2
Peak-to- peak Jitter 1 2 4 5 9
most important configuration variables are the switching
thresholds and the current limitations.
Fig. 4. Charge-Pump DLL simulation model in Simulink. The VCDL The C-element was modeled as an ideal unit, resorting to a
simulated had four controlled delays. Noise sources were assumed as additive digital description of its function. This model does not have
gaussian. configurable parameters. Fig. 3 presents the model for the C-
element, as way of illustration.
III. SIMULATION AND BEHAVIORAL MODELS The phase detector was implemented with this element and
The conceptual model presented in Fig. 1 has been used some digital logic. A custom-designed rate limiter modeled
for deriving behavior models, implemented using Matlab and the charge-pump operation. The up and down charge currents
Simulink ®. These models are used to explore design choices of the CP (always assumed equal, as is usually desired in CP
of several DLL parameters, and validating theoretical design) are configurable, as well as the initial output voltage,
conclusions extracted from the analytical models. for convergence speed-up considerations.
The Simulink model was derived using a “continuous” time Noise sources were added to these units, assuming additive
approach: simulators current capabilities allow for the usage voltage noise. Following the diagram depicted in Fig. 2,
of time-domain simulation to confirm our discrete time these (normalized) noise sources were transformed in jitter
approximations. Convergence problems (and a DLL naturally values both for the input clock jitter and the VCDL internally
presents an algebraic loop, which complicates simulation) can generated jitter. Fig. 4 shows the total simulation circuit
be mostly solved by the usage of fixed-time methods with used, with the several jitter sources clearly identified. The
small time steps – at the cost of simulation efficiency. input jitter generation is clearly presented in the upper side.
Nevertheless, we have used simulation steps of 1ps with good Simulations were run on this model quite effectively, and total
simulation times in high-performance PCs. output jitter could be calculated for typical DLL parameters,
passing the output simulation back into Matlab.
The blocks modeled were based on design insights from a
real DLL design and assumed a phase detector with a Müller The jitter introduced by these additive voltage noises in the
C-element . Thus three custom blocks were completely delay line is not expected to be of major importance, as large
designed: a line delay element, a Müller C-element, and a gain inverters are used in delay elements, which filters circuit
charge-pump. Noise sources and signal processing were noise effects. The effect of these noise sources in the phase
implemented with exiting Matlab toolboxes. Voltage and of the clock signal is small, and thus, from (7) and (8), output
time values were normalized (to 1V and 1ns, respectively). jitter is expected to be low. This has been shown in our
simulations, and with reasonable values of noise, both input
The delay element was modeled as a Matlab transport and internally generated jitter led to negligible output jitter.
delay, followed by a strangled current output block. An ideal
threshold comparator is included at the output, as large gain These two situations imply that the total size of the VCDL
inverters are common on real delay elements outputs to is not much relevant (in a first approximation) to jitter
increase edge slopes. These blocks are configurable, and the mechanisms in a DLL. Many delay elements can theoretically
be connected serially (and this is a trend in clock distribution understanding of the DLL and its performance in terms of
circuits) without large increase in clock jitter – as long as no jitter, providing insight for challenging high frequency
jitter appears in the line. If a delay element introduces jitter designs. This model has also been extended to a behavioral
in the clock, then all VCDL elements will propagate this model in Matlab.
jittered signal, and all VCDL connections after this element
will have large jitter values. The feedback mechanism in the Simulations were run on this model quite effectively, and
DLL will not reduce this jitter. total output jitter could be calculated for typical parameters.
These results have been confronted with those achieved by
The situation is even more demanding with noise in the the sampled-time model, and have been found to be in general
control voltage. Output jitter appears immediately, even with concordance.
low noise values, as Fig. 5 illustrate. Simulations also
showed, in accordance with (6), that output jitter increases The model shows that, for typical design parameters, input
linearly with this noise, as presented in Table I (discrepancies jitter and jitter internally generated by delay elements are
are due to numerical precision). almost unaffected by the DLL. This jitter will be kept in the
line as it appears in the clock. Furthermore, our model shows
Thus it is of great importance to avoid noise in the control that voltage control induced jitter plays an important part on
voltage node, as it may impair overall DLL performance. It the total output jitter, and any electrical noise in this node will
should be noted that, even in a noiseless circuit, the charge- create jitter in the clock signal. These considerations present
pump behavior leads to the existence of noise in this node , some constraints on present trends in using DLL-based
which should be minimized. architectures for high frequency clock distribution.
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