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					Prototype Deployment of
Internet Scale Overlay Hosting


Patrick Crowley and Jon Turner
and John DeHart, Mart Haitjema Fred Kuhns,
Jyoti Parwatikar, Ritun Patney, Charlie Wiseman,
Mike Wilson, Ken Wong, Dave Zar
Computer Science & Engineering
Washington University
www.arl.wustl.edu
Project Objectives                            Control Processor


       CP        GPE        GPE         NPE
 net                                          External Switch
FPGA


 External
                       Chassis Switch
                                              Network Processing Engine
  Switch
                                              Line Card
                                              General Purpose Processing Engines
                         Line Card

                                              Chassis Switch
                        10x1 GbE

 Deploy     five experimental overlay hosting platforms
  » located at Internet 2 PoPs
  » compatible with PlanetLab, moving to GENI control framework
  » performance characteristics suitable for service deployment
       • integrated system architecture with multiple server blades
       • shared NP-based server blades for fast-path packet processing
 Demonstrate          multiple applications                                       2
Role in Cluster B
                    • Overlay Hosting Platform
                    • Deployed at 5 locations
                    • Serve as backbone linking
                      cluster partners (and others)
                    • Demonstrate high quality
                      service delivery on overlays
                    • Managed using experiment
                      support tools




                                                      3
Target Internet 2 Deployment




                               2
              2
                                   3
                           2
                   2

              3        3




                                       4
Hosting Platform Details




                                                                       VM
                                                                            VM
                                                                                 ...


                 CP             GPE       GPE          NPE                  PLOS
          net
         FPGA
                                                                      General Purpose
                                                                     Processing Engine
            External
                                      Chassis Switch
             Switch



                                        Line Card       parse      lookup   header     queues
                                                                            format
Line Card




                                                                                         ...
                                                             ...                 ...
                       filter
       ...
                                       10x1 GbE


      filter            ...                               Network Processing Engine

                                                                                                5
Application Framework
                                                           Remote Login Interface
   Fastpath/slowpath
    » fastpath mapped onto NPE
                                                                       Slice
    » slice manager in vServer                                       Manager
                                                                   (in vServer)
      on GPE




                                                                                                exception packets
                                                                                                & in-band control
                                   exception packets
                                   & in-band control
                                                                GPE
   Configurable elements
    » code option – determines
                                                                   Control Interface
      how packets processed by
      parse, header format
                                                                   Filters
    » logical interfaces




                                                                                              interfaces
       • may be public or tunnel
                                   interfaces




                                                                                                output
                                                                              Header




                                                                                                  ...
                                                                                        ...
                                      input


                                                        Parse      Lookup
                                        ...

       • guaranteed bandwidth                                                 Format
                                                                               Queue
    » TCAM filters                                     Fast Path              Manager
    » Queues
       • length, bandwidth
 Slice   manager can configure fastpath using provided library
    »or manually, using command line interface
                                                                                                                    6
Creating a Slice
                    PLC


    CP                    GPE   GPE              NPE
              SRM

      net
     FPGA




         External
                                Chassis Switch
          Switch




                                  Line Card




                                                       7
Starting up a Slice

               Logging into slice

     CP                     GPE     GPE              NPE
               SLM

       net
      FPGA




          External
                                    Chassis Switch
           Switch


                                                       Requires Network
     SFTP connection for                              Address Translation
     downloading code                 Line Card       datapath detects new
                                                      connection, LC control
                                                      processor adds filters



                                                                               8
Configuring an External Port
                             GPE            GPE              NPE

         CP
                   SRM

           net                               RMP
          FPGA




              External
                                            Chassis Switch
               Switch


● Request external port number on           LC
  specific interface thru Resource
  Manager Proxy (RMP)
● RMP relays request to System
  Resource Manager (SRM)
● SRM configures LC filters for interface
● Arriving packets directed to slice,
  which is listening on socket
                                                                   9
Setting Up a Fast Path
                          GPE        GPE            NPE
                                                      parse   lookup   header   queues
        CP                                                             format
                  SRM




                                                                                   ...
          net                        RMP
         FPGA




             External
                                                Chassis Switch
              Switch


                                           LC
● Request fastpath through RMP
● SRM allocates fastpath
● Specify logical interfaces and
  interface bandwidths
● Specify #of filters, queues, binding
  of queues to interfaces, queue
  lengths and bandwidths
● Configure fastpath filters
                                                                                         10
Planned Wide-Area OpenFlow




                                                                     hdrFmt
                                                            lookup


                                                                              queue
                                                    parse
                                   net   CP   NOX
                                  FPGA




            NOX
                                                                                                   Princeton


                  to SPP                               WashU
 Stanford
                                                                                      2
                           2
                                                                                          3
                                                                     2
                                              2                                           GaTech

                           3                                    3



                               Texas

                                                                                                               11
NP Blade                                            Loc. Mem.




                                                                      contexts
                                                                       thread
                               SRAM                            ...
                                       SDRAM




                                                         TC
                                                    TC
                                                         ALU
  NP A
                                    Mem
            ME

                 ME




                               ME
                       ...
                                    Int




                                                                                 Interfaces
                                                                                  External
                                                                     RTM
                                    TCAM
                      xScale
    input                            Int   output

                      SPI Switch    TCAM




                                                                                 Interface
                                                                                  Switch
                                                                     FIC
  NP B

                                                                                              12
           Line Card Datapath
                                      DRAM
                                                          SRAM                       SRAM

                                            Key                             Hdr      Queue
                          RxIn                            Lookup                                TxIn
external interfaces




                          (2 ME)           Extract        (2 ME)          Format    Manager    (2 ME)
                                            (2 ME)                        (1 ME)     (4 ME)




                                                                                                        switch interface
                         ingress side
                                                                   TCAM
                         egress side

                                   Flow         Queue         Hdr                     Key
                      TxEg                                                Lookup               RxEg
                      (2 ME)       Stats       Manager      Format         (2 ME)    Extract   (2 ME)
                                   (2 ME)        (4 ME)     (1 ME)                   (1 ME)


                                   SRAM          SRAM       SRAM
                                                                                       DRAM

                   Filter/route and rate-control traffic
                   Network Address Translation for outgoing flows
                   Record traffic statistics for all outgoing flows
                                                                                                                13
NPE Datapath (version 1)
                        DRAM
                                 SRAM               SRAM
                                                    SRAM

              Substr.                       Hdr     Queue
    Rx                  Parse    Lookup                       Tx
   (2 ME)     Decap     (1 ME)   (1 ME)   Format   Manager   (2 ME)
              (1 ME)                      (1 ME)    (4 ME)


                        SRAM     TCAM


 Parse     and Header Format include slice-specific code
  » parse extracts header fields to form lookup key
  » Hdr Format does any required post-lookup processing
 Lookup  uses opaque key for TCAM lookup
 Multiple static code options can be supported
  » multiple slices per code option
  » each has own interfaces, filters, queues and private memory
                                                                      14
NPE Datapath (Version 2)
                                        SRAM
                                       SRAM
    from switch




                   Rx       Decap, Parse, Lookup, AddShim            Tx
                  (2 ME)               (8 MEs)                    (2 ME)


                                        TCAM
                                                                          SPI Switch


                                       Queue     Lookup
    to switch




                     Tx     HdrFmt                           Rx
                   (2 ME)   (4 MEs)   Manager    & Copy     (2 ME)
                                      (4 MEs)    (2 ME)


                                       SRAM
                                      SRAM       SRAM


 Use both NPs, enabling 10 Gb/s throughput
 Integrated Decap,Parse,Lookup uses MEs more efficiently
 Multicast supported by substrate
                                                                                       15
Project Plan Highlights
 Initial   deployment
  » first two (maybe three) nodes deployed by mid 2009
  » shooting for v2 of NPE software
  » PlanetLab control with local resource allocation
 GENI-compatible     control software
  » implement component manager interface
  » resource allocation using rspecs/tickets
 Working     with users
  » online and hands-on tutorials
  » collaborating with users on new code options
 Completing    deployment
  » final nodes deployed in late 2010
  » complete support for netFPGA
                                                         16
Looking Ahead
 Bad   news
 » slow market for ATCA means high cost, limited support
 » Intel dropped IXP and Radisys discontinuing IXP blades
 Good   news
 » ATCA market now projected to grow rapidly and become
   more cost-competitive (10x growth over 3 years)
 » new NPs and NP blades
   • Netronome 3200 – IXP successor with 40 microengines
   • Cavium Octeon, RMI XLR732 – MIPS-based, uses cache
 » can also assemble systems from commodity components
   • 10 GbE switches now at $400-500 per port
   • conventional rack-mount servers with 8-16 processor cores
   • NPs and FPGAs on lower cost PCI-express cards
                                                                 17

				
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