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www.lnf.infn.itcommitteetalks29i Powered By Docstoc
					         Mihai Iliescu

          on behalf of

  the SIDDHARTA collaboration




LNF SCIENTIFIC COMMITTEE
     8-9 November 2004
              Contents

1   SDD production

2   Detectors mounting: ceramics and bonding

3   Experimental setup

4   Kaon trigger

5   Front-end electronics

6   Implementation plan
     1.State of fabrication of large SDD array for the SIDDHARTA
                                   project
                                   (PNSensor, Munich)

 Front side of the chip: electronic side with the drift rings
  fully finalized: implantation of the transistors; drift rings (including their intrinsic
  resistive connection); bulk contact; temperature diode; annealing
  Deposition of protecting and isolating dielectric layers finalized within mid
  November


 Back side of the chip:
   Back side structuring; implantation and annealing will start when the deposition of
  protecting layers of the front side will be finalized: first control measurements of
  leakage current performed at that moment
  Nitride structuring within end 2004; aluminium deposition and structuring on the
  precursor wafers will start at the beginning 2005
1.State of fabrication of large SDD array for the SIDDHARTA
                              project
                           (PNSensor, Munich)



 Electrical testing and cutting of the first wafers by the end of
  January 2005


 Dummy chips for supporting the substrate fabrication and testing the
mounting and bounding issues already delivered to the Vienna group


 30 mm2 prototype chip delivered for testing to the Frascati group
SDD production status


SDD layout – readout side



      chip size: 34 x 14
             mm²


         sensitive area

           3 x 100
            mm²

integrated temperature
sensors
SDD layout – readout side, cell center




                                                  •   bond pads
              inner         feedback
            substrate       capacitor                   150 x 150 µm²
                                                        @ R ≈ 350 µm
  150 µm
                                         source   •   7 internal contacts
                                                        - source
   ring_1
                                                        - drain
                                                        - ring_1
                                          reset
                                          diode         - inner guard ring
    R=                                                  - inner substrate
  350 µm     inner
                                                        - reset diode
             guard
                              drain                     - feedback cap. ~ 10 fF
              ring
SDD drift time vs. temperature
Test in the laboratory of a 30mm2 SDD chip



                             4000




                             3000




                    Counts
                                                   139 eV FWHM
                             2000




                             1000




                               0
                               5000   5500       6000       6500   7000
                                             Energy [keV]

                                      T = - 40°C, tsh=0.75ms
2. Detectors mounting: ceramics and bonding

  SDD bonding scheme – readout side
SDD-ceramic, bonding
                                            KERAMIK 1   KERAMIK 2
Status:
• 20 pieces of high purity prototype
  ceramic boards are ready
• first gluing test with SDD-dummies into
  the high purity ceramic boards;
• start of this tests mid of November
  2004, at the Fraunhofer Institute,
  Berlin
• cryogenic tests of the glued
  SDD-dummy – ceramic board
  at SMI, Vienna
• perform first bonding tests with
  SDD-dummies, to extract the
  final working parameters
• inspection of the bonding tests
  at MPI-Halbleiterlabor, Munich
  and SMI, Vienna
                    3. Experimental setup
                                    target
                                    cooling line



feed-throughs for                                  port for
SDD electronics                                    SDD cooling



SDD pre-amplifier                                   vacuum chamber
electronics
                                                          lead table

SDD detector
chip




                                                          target cell


   beam pipe
SDD mounting layout
(Vienna group)

                            cooling target cell
     pre-amplifier
     and voltage
     supply boards


                                                  SDD cryogenic
                                                  mounting device




                      beam pipe
Cryogenic target cell (prototype)              target
                                               cooling
Status:
Prototype under construction at
SMI, Vienna




                                                            SDD window
                                                            50 µm kapton



                                                            thin-walled
               kaon entrance window                      aluminum body
                  125 µm kapton

                                      100 mm
                             4.Kaon trigger
                             (Frascati group)

Time of flight spectrum in the DEAR kaon monitor


                1450 ps




                                                DEAR baseline: 10.5 cm
                                                SIDDHARTA baseline: 5.0 cm




         (tdc3+tdc4)/2 [50ps/ch]
                              Timing resolution improvement:


                        Selection of PMT and Scintillating Material

     PMT Type              Max.            Gain          Anode Pulse Rise   Electron Transit     Transit Time
                        Voltage [V]                         Time [ns]          Time [ns]         Spread [ns]
  Philips XP2020           2500           4x107                 1.5               30                 0.55

Hamamatsu R4998            2500           5.7x106               0.7               10                 0.16




Scintillator Material   Peak Wavelength             Rise Time           Decay Time         Attenuation length
                             [nm]                      [ns]                [ns]                  [cm]
      NE104                    406                     0.6                  1.8                   120

      BC420                    391                     0.5                  1.5                   110



               A prototype equipped with 4 Hamamatsu R4998 PMTs
               shall be ready for testing within February 2005
Preliminary scintillator array topology (Monte Carlo simulation)




                                         3
                                  2 1


                                                             beam pipe
                             6
                         4
                     5
                                  Entries



                     Uncorrelated hits




                                        1- 4
                                 1- 5
                          1- 6




                          2-4




Slab pairs
                   2-5
             2-6
                                               Simulated Coincidence Pattern




                          3-4
                    3-5
                   3-6
Simulated kaons arrival time




                                          Pattern:
                                      1.and.(4.or.5.or.6)




      TDC Slab 1               [ps]
Trigger tests on an array of 7 x 5 mm2 SDD chips at Frascati Beam Test Facility


                                         SDD array: 7 x 5 mm2 chips
                                                                            Fluorescence X- rays

                                                                  Fe55

               Scintillator


   e- beam                                             Sr90
   from BTF                                                              Excited material




                              Pb slab   e.m. shower
Incident rate: 60 Hz on 7 channels => 8.5 Hz/channel
                                                  a)   # Trigger OFF (16 hours.)
                                                       # Cu signal visible;
                                                       # No asynchronous backg (55Fe and 90Sr)
                                                       # Continuous background:
                                                         - synchronous from primary beam
                                                       # 5 Hz

                                                  b)   # Trigger OFF (20 min.)
                                                       # Cu signal embedded in backg.
                                                       # Structured asynchronous backg:
                                                         - Mn Ka and Kb from 55 Fe
                                                       # Continuous background:
                                                         - synchronous from primary beam
                                                         - asynchronous from 90 Sr source
                                                       # 60 Hz

                                                  c)   # Trigger ON, 1 ms (~ 16 hours)
                                                       # Cu signal visible
                                                       # Structured asynchronous backg.
                                                         completely cut;
                                                       # Continuous background:
                                                         - synchronous from primary beam
                                                       # 5 Hz – as a)
Incident rate: 1000 Hz on 7 channels => 142 Hz/channel



                                               a)   # Trigger OFF (18 min.)
                                                    # Cu signal embedded in background
                                                    # Structured asynchronous background:
                                                      - Mn Ka and Kb from 55 Fe
                                                      - Ni Ka and Kb excited from Sr90
                                                    # Continuous background:
                                                      - synchronous from primary beam
                                                      - asynchronous from 90 Sr source
                                                     # 1000 Hz

                                               b)   # Trigger ON 1ms (~ 13 hours)
                                                    # Cu signal visible
                                                    # Structured asynchronous background
                                                      completely cut;
                                                    # Continuous background:
                                                      - synchronous from primary beam
                                                    # 5 Hz
                                                                                    5. Front-end electronics
                  1.1
                                                    5 kcounts/s
                                                                                          (Politecnico Milano)
                  1.0   (b)                       285 kcounts/s
                  0.9                             577 kcounts/s
                                                                                             Study of the stability of the SDD
                  0.8
relative height




                  0.7

                  0.6

                  0.5
                                                                                         Problem of the current configuration:
                  0.4

                  0.3                                                                    Relevant peak shift by changing the signal current.
                  0.2
                                                                                         SIDDHARTA foresees high and time-varying
                  0.1

                  0.0
                                                                                         background
                         2200         2400             2600                  2800
                                      channels
detector                chip
                                                                                             A1
                                                        drain                       R1



                            Rg                                               C1
                                        Cgd

                                                                         0

                  Iin                                       f irstf et
                                           Ctot                                                              Solution:
                                       0
                                                                                             A
                                                                                                     Vout
                                                                                                             Use of the SDD-JFET system
                        0        Cf                         source
                                                                                         -
                                                                                                             in a Charge Preamplifier
                                                                                                             configuration
                                                    -v cc
                             Scheme with CSA for improved stability


                                    C1                                           BLH
                                         HV
                                         drain   A1         External A1 adjustment
                                                            for P/Z
                                                            cancellation
                      Rd

       Isignal                      Cstray        Pre
                                                  out
                       CF                 R              P/Z             Shaper             out
                                                          fixed



         Detector chip                                            FE chip
• Charge preamplifier (CA), instead of source follower + voltage preamplifier, for better stability
• Design issues: same resolution as conventional configuration, insensitivity to stray capacitances
of the connections (critical for CA), JFET drain high-voltage driving, ext. pole-zero adjustement
• Same unipolar and bipolar shaping circuits as in the conventional configuration
• Improved rejection of baseline shifts by means of suitable Baseline Holder
Results from simulations of the VLSI analog channel with Charge Preamplifer




              Cstray: 0-30pF




     Preamplifier rise time




                                          Shaper output with baseline restorer
 Gain stability measurements in the LNF laboratory with the charge amplifier

                        6020




                        6000




                        5980
Position Mn line (eV)




                        5960

                                   Max expected
                                   background rate
                        5940




                        5920




                        5900




                        5880
                               0           200       400   600         800          1000         1200    1400   1600   1800
                                                                             Rate (Hz)

                                                             with charge amp        without charge amp
            Resolution measurements in the LNF laboratory with the charge amplifier

            350



            330



            310



            290



            270
FWHM (eV)




            250



            230



            210



            190



            170



            150
                  0   200   400     600            800          1000         1200   1400   1600   1800

                                                         Rate (Hz)
                                          with charge amp    without charge amp
I run layout (submitted on 15 August 2004, ready mid Nov. 2004)



                                                  Charge preamplifier
                                                  + shaper
                                                  (0.6-0.8-1.5-3ms peak times)



                                                  Source follower
                                                  + voltage preamplifier
                                                  + shaper
                                                  (0.6-0.8-1.5-3ms peak times)



                                                   Charge preamplifier
                                                   + shaper
                                                   (0.8-1-2-4ms peak times)
SDD Bias Voltage Controller to enhance detector gain stability


                                                  Prototype to be used on the
                                                  30 mm2 SDD chip, under
                                                  development at IFIN Bucharest

                                                  Characteristics:

                                                  •Communication: USB 1.1

                                                  •DSP board (Analog Devices)

                                                  •Two Programmable A/D, D/O
                                                  loops:

                                                   9010V (16 bit accuracy /20V)

                                                   19010V (16 bit accuracy /20V)
                         6.Implementation plan of the SIDDHARTA experiment
                           Implementation plan: SIDDHARTA PROJECT                                                                    5 November 2004
                   Deliverables / Tasks            2004         2005                                                                      2006
                                                                  1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

Large area SSD
SDD fabrication procedure; production
Start test on fabrication, including spectroscopic charact.
Electrical characterization and selection of chips
Second fabrication run
Front-end electronics
Design front-end electronics (I); production and test 1st run
Design front-end electronics (II); production and test IInd run
Production all electronics; engineering run
DAQ and trigger
Design prototype and test
Realization, assembling and test
Setup
Design of experimental setup
Realization of mechanical and cryogenic components
Assembling, test, installation
Assembling large area SDD setup
Test on BTF at LNF
Installation and debugging on DAFNE