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					Minute of the meeting on interfacing the GTK demonstrators to a “demonstrator” DAQ system

CERN, Sept 02 2008

       Pierre Jarron, Flavio Marchetto
       Eduardo Cortina
       Elena Martin
       Pierre Jarron
       Alexander Kluge
       Sakari Tiuraniemi
       Flavio Marchetto
       Giulio Dellacasa
       Gianni Mazza
       Angelo Cotta Ramusino

       The main topics were:
1. to analyze in detail the present implementation of the output blocks of the CERN and the INFN-
   TO GTK demonstrator ASICs to see if they could be made similar from the point of view of the
   DAQ system.
2. to outline the requirements for the physical connection between the GTK demonstrators and the
   “sensor proximity” card hosting the resources needed for the ASIC operation and readout, such
   as a “Front-End” FPGA, PLL, DACs, a high speed link (optical / electrical) driver and
   eventually a USB2.0 or Ethernet port
3. to discuss about how Elena Martin, engineer from Université Catholique de Louvain, could
   contribute to the project with her expertise in electronic design

    TO GTK ASIC has a 1.2V supply for the I/O meanwhile the CERN GTK ASIC uses 2.5V
       while LVDS standard is fine for the CERN ASIC the 1.2V common mode voltage of the
      LVDS is too high for the TO ASIC
       ACTION ITEM(1): find out whether the TO ASIC needs to use the 2.5V I/O as well or it
      is possible to interface the “Front End” FPGA to a differential standard operating @ 1.2V
    TO GTK ASIC input clock frequency is 160MHz while the CERN ASIC’s is 320MHz
       make sure that the PLL on the “sensor proximity” card produces both
       alternatively TO could implement a frequency divider
    An LVDS “SYNCH” signal is provided to the ASICs to define the origin of time
      measurements: the TDCs start measuring time from the first rising edge of the clock
      following the return to the unactive state of the “SYNCH” signal
    in addition a CMOS level reset signal will be provided by the “proximity” card as a general
      ASIC reset
    The interface to the “Front End” FPGA for the TO GTK ASIC is represented by 3 ports with
      parallel data (16 bit) and flow control signals as described in Giulio’s presentations.
      ACTION ITEM(2): evaluate if the number of pads available on the demonstrator allow for
      differential or single ended standard for the 16 parallel data bus, because this might put
      different constraints on the “proximity card” board architecture and layout
    The interface to the “Front End” FPGA for the CERN GTK ASIC is represented by 9 ports
      with a serial transmission protocol based on:
             o an LVDS serial data output. ACTION ITEM(3): the size of the data word is to be
                  defined, since it was suggested to increase the size of the coarse counter from the
                  present 6 bit to a length consistent with the dynamic range of the TO GTK ASIC,
                  which has 10bit of coarse counter + 16 bits of frame Number as shown in “In pixel
                  TDC demonstrator chip: status of the end of column readout” G. Dellacasa, GTK
                  WG meeting, May27th 2008.
             o a CMOS “DATA READY” output to flag the “Front End” FPGA that a new
                  measurements is ready to be captured
             o an LVDS “Shift Clock” input driven by the FPGA to shift out data from the CERN
                  GTK output register
             o a CMOS “READ DONE” input driven by the “Front End” FPGA to tell the GTK
                  ASIC that the output register has been read out
         ACTION ITEM(4): To partially overlap the readout and timing measurement operations it
         was proposed to implement a second output register on each port, which would be written as
         the first one is being readout. CERN designer should decide whether it is feasible within the
         project contraints.
        it seems convenient to bond the GTK ASICs onto passive (eventually equipped with local
         power supply filtering) “carrier” boards to be connected to the “sensor proximity” card.
         This”proximity card” would host the resources needed for the ASIC operation and readout,
         such as a “Front-End” FPGA, PLL, DACs, voltage regulators/references (paying attention to
         the radiation environment) a high speed serial link (optical / electrical) and eventually a
         USB2.0 or Ethernet port for stand alone operation.
         ACTION ITEM(5): find a suitable interconnect system compliant to the bandwidth required

       a possible contribution from Elena Martin, engineer from Université Catholique de Louvain,
        could be in the development of the sensor proximity cards, a task which would be shared
        with the INFN Ferrara.
      to start the development of this item it would be necessary to collect from the GTK ASICs
        designers a “close to final” set of specifications on:
            o chip pinout
            o signalling speeds and standards
            o data transfer portocol
        A good time to sign off on this specifications would be the scheduled “Design Review”

                                              minutes edited by:
                                              Angelo Cotta Ramusino

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