An Introduction to the Amplify Physical Optimizer
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An Introduction to the Amplify Physical Optimizer ™ ™
by Steve Pereira,Technical Marketing Manager
The Amplify Physical Optimizer is the How Amplify Works With Amplify software, you interactively
first and only true physical synthesis product Physical synthesis is essentially the ability assign the logic of the critical paths at the
designed exclusively for FPGAs. Amplify to use physical design characteristics, such as RTL into regions on the programmable logic
Physical Optimizer improves performance regional placement and interconnect delay, device.After you complete this phase, the
and productivity by utilizing physical design during the synthesis process to affect the physical constraints are used by the physical
information during the synthesis process.The actual topology of the circuit. Amplify optimization algorithms to optimize the design.
Amplify tool was created for programmable Physical Optimizer goes beyond what may Amplify software can also help reduce the time
logic designers utilizing high-density Altera be accomplished with floorplanning, traditional required to perform place and route, which is
and Xilinx devices who need to achieve the synthesis, and back annotation of delay especially significant as FPGA designs continue
highest performance possible.The Amplify information by producing a better (physically towards the trend of multi-million gates.
tool combines register transfer level (RTL) optimized) netlist in addition to placement. Amplify software’s output is a physically
graphical physical constraints with highly Floorplanners can only create placement for optimized netlist that is ready for place
innovative new algorithms that perform an already synthesized netlist. The Amplify and route, along with a set of constraints
placement and logic optimization on your tool features an innovative user interface for containing placement information in a format
circuit simultaneously. creating physical constraints that help increase accepted by the Altera and Xilinx back-end
the overall timing performance of a design place and route tools.
while reducing the amount of iterations typically
% of path Delay
Wires (Routing) necessary to meet timing requirements. When Should I Use Amplify?
One of the Amplify product’s main There are certain circumstances that offer
functions is to provide you with feedback on the greatest performance improvement when
your specific design that will help you create using the Amplify tool. Typically, designers are
50% Cross-over at 0.25µ an optimal set of physical constraints.The seeing between 10% and 35% improvement in
intuitive graphical user interface allows you to critical path performance when the following
easily communicate these physical constraints design criteria applies:
to synthesis for physical optimization, and • Larger designs. The larger the design the
Logic (LUTs) create placement for the place and route greater the improvement in performance.
.25µ .18µ .13µ tool.An HDL design has much less detail • When the design isn’t meeting the
CMOS Features length than a gate-level design, making it easier required frequency. Use the Synplify Pro™
Figure 1 to partition the design and make region tool if the speed performance is being
assignments. Because physical constraints are met and you want to reduce area.
Why is Physical Synthesis available earlier in the flow, the Amplify tool • Where the critical paths are largely
Needed? can restructure logic based on information caused by routing delays. Amplify
With FPGAs and CPLDs reaching 2 Million inside and between regions, yielding higher Physical Optimizer can really improve
system gates an interesting phenomenon has performance circuits. performance when routing delays
occurred. With gate length (Leff) becoming are predominant.
increasingly smaller and dies becoming larger,
the proportion of LUT/Register delays to the
total path delay is decreasing, but the routing
delays are getting much larger. Hence, routing
delays are now significantly affecting path
delays more than ever before. (See Figure 1.)
With gate counts making their way up to 4
million gates (and the prospect of reaching 10
million gates by the end of the year), routing
delays are fast becoming the problem.
Xilinx chip view in the Amplify tool environment Altera chip view in the Amplify
tool environment
The Amplify tool is also designed to provide
• Incremental Design. With the traditional
flow of synthesis then floorplan, any code
modifications require re-synthesis and
re-floorplan. With the Amplify tool the
physical constraints are maintained so
re-floorplanning is obsolete.
• Team Design methodology.
• Short time-to-market.
• A slower speed grade part.
And Finally…
With FPGAs and CPLDs destined to hit
the 10 million-gate mark, the working design
methodology must change with the climate.
Wire delays have an enormous impact on
design performance. With entire teams (10
plus engineers) now dedicated to one FPGA,
team and incremental design are essential to
get the product to market. The Amplify
Physical Optimizer answers all these pressing
questions, with an amazingly intuitive and
simple user interface that is the trademark
of Synplicity.
If you have any question on the Amplify
tool or using it for your design, please visit
www.synplicity.com/amplify or call your local
Synplicity sales office.
