VIEWS: 13,701 PAGES: 35 CATEGORY: Engineering POSTED ON: 2/27/2010
VHDL PRACTICAL FILE EXPERIMENT NO. 1 AIM OF THE EXPERIMENT: To study XILINX software. THEORY: Xilinx, Inc. (NASDAQ: XLNX) is the world’s largest supplier of programmable logic devices, the inventor of the field programmable gate array (FPGA) and the first semiconductor company with a flawless manufacturing model. Founded in Silicon Valley in 1984 and headquartered in San Jose, California, U.S.A.; Dublin, Ireland; Singapore; and Tokyo, Japan, the company has corporate offices throughout North America, Asia and Europe. The programmable logic device market has been led by Xilinx since the late 1990s. Over the years, Xilinx has fueled an aggressive expansion to India, Asia and Europe – regions Xilinx representatives have described as high-growth areas for the business. Xilinx’s sales rose from $560 million in 1996 to almost $2 billion by 2007. The relatively new President and CEO Moshe Gavrielov – an EDA and ASIC industry veteran appointed in early 2008 – aims to bolster the company’s revenue substantially during his tenure by providing more complete solutions that align FPGAs with software, IP cores, boards and kits to address focused target applications. The company aims to use this approach to capture greater market share from application-specific integrated circuits (ASICs) and application-specific standard products (ASSPs). The company’s products have been recognized by EE Times, EDN and others for innovation and market impact.The company has expanded its product portfolio substantially since its founding, now selling a broad range of FPGAs, complex programmable logic devices (CPLD), design tools, intellectual property and reference designs.Xilinx also has a global services and training program.The organization’s most popular product lines (see Current Family Lines) are the Spartan, Virtex and EasyPath series, each including configurations and models optimized for different applications. VHDL PRACTICAL FILE Technology Xilinx designs, develops and markets programmable logic products including integrated circuits (ICs), software design tools, predefined system functions delivered as intellectual property (IP) cores, design services, customer training, field engineering and technical support. Xilinx sells both FPGAs and CPLDs programmable logic devices for electronic equipment manufacturers in end markets such as communications, industrial, consumer, automotive and data processing. Current Family Lines Xilinx has two main FPGA families: the high-performance Virtex series and the high- volume Spartan series, with a cheaper EasyPath option for ramping to volume production. It also manufactures two CPLD lines, the CoolRunner and the 9500 series. Each model series has been released in multiple generations since its launch. Spartan Family The Spartan series targets applications with a low-power footprint, extreme cost sensitivity and high-volume such as displays, set-top boxes, wireless routers and other applications. The Spartan-6 family is built on a 45-nanometer (nm), 9-metal layer, dual- oxide process technology. The Spartan-6 was marketed in 2009 as a low-cost solution for automotive, wireless communications, flat-panel display and video surveillance applications. The Spartan-3A consumes more than 70-90 percent less power in suspend mode and 40-50 percent less for static power compared to standard devices. Also, the integration of dedicated DSP circuitry in the Spartan series has inherent power advantages of approximately 25 percent over competing low-power FPGAs. RESULT: XILINX software has been carefully studied. VHDL PRACTICAL FILE EXPERIMENT NO. 2a AIM OF THE EXPERIMENT: To implement AND gate using XILINX Software. THEORY: The AND gate is a digital logic gate that implements logical conjunction - it behaves according to the truth table to the right. A HIGH output results only if both the inputs to the AND gate are HIGH. If neither or only one input to the AND gate is HIGH, a LOW output results. INPUT OUTPUT A B A AND B 0 0 0 0 1 0 1 0 0 1 1 1 VHDL PROGRAM: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; VHDL PRACTICAL FILE entity and222 is Port ( a : in STD_LOGIC; b : in STD_LOGIC; c : out STD_LOGIC); end and222; architecture Behavioral of and222 is begin process(a,b) begin if((a='1')and(b='1'))then c<='1'; else c<='0'; end if; end process; end Behavioral; RESULT: The AND gate has been successfully designed and implemented on XILINX SPARTAN KIT. VHDL PRACTICAL FILE EXPERIMENT NO. 2b AIM OF THE EXPERIMENT: To implement OR gate using XILINX Software. THEORY: The OR gate is a digital logic gate that implements logical disjunction - it behaves according to the truth table to the right. A HIGH output results if one or both the inputs to the gate are HIGH. If neither input is HIGH, a LOW output results. INPUT OUTPUT A B A+B 0 0 0 0 1 1 1 0 1 1 1 1 VHDL PROGRAM: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity or222 is Port ( a : in STD_LOGIC; b : in STD_LOGIC; c : out STD_LOGIC); end or222; VHDL PRACTICAL FILE architecture Behavioral of or222 is begin process(a,b) begin if((a='0')and(b='0'))then c<='0'; else c<='1'; end if; end process; end Behavioral; RESULT: The OR gate has been successfully designed and implemented on XILINX SPARTAN KIT. VHDL PRACTICAL FILE EXPERIMENT NO. 2c AIM OF THE EXPERIMENT: To implement XOR gate using XILINX Software. THEORY: The XOR gate is a digital logic gate that implements exclusive disjunction - it behaves according to the truth table above. A HIGH output results if one, and only one, of the inputs to the gate is HIGH. If both inputs are LOW or both are HIGH, a LOW output results. INPUT OUTPUT A B A XOR B 0 0 0 0 1 1 1 0 1 1 1 0 VHDL PROGRAM: library IEEE; use IEEE.STD_LOGIC_1164.ALL; VHDL PRACTICAL FILE entity xor222 is Port ( a : in STD_LOGIC; b : in STD_LOGIC; c : out STD_LOGIC); end xor222; architecture Behavioral of xor222 is begin process(a,b) begin if((a='1')and(b='1'))then c<='0'; elsif((a='0')and(b='0'))then c<='0'; else c<='1'; end if; end process; end Behavioral; RESULT: The XOR gate has been successfully designed and implemented on XILINX SPARTAN KIT. VHDL PRACTICAL FILE EXPERIMENT NO. 3 AIM OF THE EXPERIMENT: To implement XOR gate using XILINX Software. THEORY: The XOR gate is a digital logic gate that implements exclusive disjunction - it behaves according to the truth table above. A HIGH output results if one, and only one, of the inputs to the gate is HIGH. If both inputs are LOW or both are HIGH, a LOW output results. OUTPUT INPUT A XOR B A B 0 0 0 0 1 1 1 0 1 1 1 0 VHDL PROGRAM: Library IEEE; Use ieee.std_logic_1164.all; VHDL PRACTICAL FILE Entity xor_2 is Port(a,b:in bit; z: out bit); End xor_2; Architecture xor_2 of xor_2 is Begin Process (a,b) Variable abar, bbar,x,y; Begin Abar:=not a; Bbar:=notb; X:=abar and b; Y:= bbar and a; Z<=x or y; End process; End xor_2; RESULT: The XOR gate has been successfully designed and implemented on XILINX SPARTAN KIT. VHDL PRACTICAL FILE EXPERIMENT NO. 4 AIM OF THE EXPERIMENT: To implement DECODER gate using XILINX Software. THEORY: A decoder is a multiple-input, multiple-output logic circuit that converts coded inputs into coded outputs, where the input and output codes are different. e.g. n- to-2n, BCD decoders. Enable inputs must be on for the decoder to function, otherwise its outputs assume a single "disabled" output code word. VHDL PROGRAM: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; VHDL PRACTICAL FILE entity decorder222 is Port ( a : in STD_LOGIC_vector(1 downto 0); x : out STD_LOGIC_vector(3 downto 0)); end decorder222; architecture Behavioral of decorder222 is begin process(a) begin case a is when "00"=>x<="0001"; when "01"=>x<="0010"; when "10"=>x<="0100"; when "11"=>x<="1000"; when others=>x<="0000"; end case; end process; end Behavioral; RESULT: The DECODER has been successfully designed and implemented on XILINX SPARTAN KIT. VHDL PRACTICAL FILE EXPERIMENT NO. 5 AIM OF THE EXPERIMENT: To implement HALF ADDER gate using XILINX Software. THEORY: A half adder is a logical circuit that performs an addition operation on two binary digits. The half adder produces a sum and a carry value which are both binary digits. A B C S 0 0 0 0 0 1 0 1 1 0 0 1 1 1 1 0 VHDL PRACTICAL FILE VHDL PROGRAM: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity hadder is Port ( a : in STD_LOGIC; b : in STD_LOGIC; sum : out STD_LOGIC; carry : out STD_LOGIC); end hadder; architecture Behavioral of hadder is begin process(a,b) begin if((a='0')and(b='0'))then sum<='0'; carry<='0'; elsif((a='0')and(b='1'))then sum<='1'; carry<='0'; elsif((a='1')and(b='0'))then sum<='1'; VHDL PRACTICAL FILE carry<='0'; elsif((a='1')and(b='1'))then sum<='0'; carry<='1'; end if; end process; end Behavioral; RESULT: The HALF ADDER has been successfully designed and implemented on XILINX SPARTAN KIT. VHDL PRACTICAL FILE EXPERIMENT NO. 6 AIM OF THE EXPERIMENT: To implement HALF SUBTRACTOR gate using XILINX Software. THEORY: A half subtractor is a logical circuit that performs an subtraction operation on two binary digits. The half subtractor produces a difference and a borrow value which are both binary digits. A B DIFF BORROW 0 0 0 0 1 0 1 0 0 1 1 1 1 1 0 0 VHDL PROGRAM: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; entity hsub is Port ( a : in STD_LOGIC; b : in STD_LOGIC; sub : out STD_LOGIC; borrow : out STD_LOGIC); end hsub; VHDL PRACTICAL FILE architecture Behavioral of hsub is begin process(a,b) begin if((a='0')and(b='0'))then sub<='0'; borrow<='0'; elsif((a='0')and(b='1'))then sub<='1'; borrow<='1'; elsif((a='1')and(b='0'))then sub<='1'; borrow<='0'; elsif((a='1')and(b='1'))then sub<='0'; borrow<='0'; end if; end process; end Behavioral; RESULT: The HALF SUBTRACTOR has been successfully designed and implemented on XILINX SPARTAN KIT. VHDL PRACTICAL FILE EXPERIMENT NO. 7 AIM OF THE EXPERIMENT: To implement FULL ADDER gate using XILINX Software. THEORY: Full adder combines two half adders to add the carry bit from the previous bit position to the sum bit. A carry bit is produced by the full adder if either of the half adders produce a carry. VHDL PROGRAM: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; entity fadder is Port ( a : in STD_LOGIC_vector(2 downto 0); z : out STD_LOGIC_vector(1 downto 0)); end fadder; VHDL PRACTICAL FILE architecture Behavioral of fadder is begin process(a) begin case a is when "000"=>z<="00"; when "001"=>z<="10"; when "010"=>z<="10"; when "011"=>z<="01"; when "100"=>z<="10"; when "101"=>z<="01"; when "110"=>z<="01"; when others=>z<="11"; end case; end process; end Behavioral; RESULT: The FULL ADDER has been successfully designed and implemented on XILINX SPARTAN KIT. VHDL PRACTICAL FILE EXPERIMENT NO. 8 AIM OF THE EXPERIMENT: To implement FULL SUBTRACTOR gate using XILINX Software. THEORY: In full adder three bits are involved in performing the subtraction for each bit: the minuend (Xi), subtrahend (Yi), and a borrow in from the previous bit order position (Bi). The outputs are the difference bit (Di) and borrow bit Bi A B C BORROW DIFFERENCE 0 0 0 0 0 0 0 1 1 1 0 1 0 1 1 0 1 1 1 0 1 0 0 0 1 1 0 1 0 0 1 1 0 0 0 1 1 1 1 1 VHDL PROGRAM: library IEEE; use IEEE.STD_LOGIC_1164.ALL; VHDL PRACTICAL FILE entity fsub is Port ( a : in STD_LOGIC_vector(2 downto 0); z : out STD_LOGIC_vector(1 downto 0)); end fsub; architecture Behavioral of fsub is begin process(a) begin case a is when "000"=>z<="00"; when "001"=>z<="11"; when "010"=>z<="10"; when "011"=>z<="00"; when "100"=>z<="11"; when "101"=>z<="01"; when "110"=>z<="00"; when others=>z<="11"; end case; end process; end Behavioral; RESULT: The FULL SUBTRACTOR has been successfully designed and implemented on XILINX SPARTAN KIT. VHDL PRACTICAL FILE EXPERIMENT NO. 9 AIM OF THE EXPERIMENT: To implement 2:1 MULTIPLEXER using XILINX Software. THEORY: In digital circuit design, the selector wires are of digital value. In the case of a 2-to-1 multiplexer, a logic value of 0 would connect I0 to the output while a logic value of 1 would connect I1 to the output. In larger multiplexers, the number of selector pins is equal to , where n is the number of inputs. S A B Z 1 1 1 1 0 1 0 0 1 0 0 0 0 1 1 1 1 0 0 1 0 1 1 0 0 0 VHDL PRACTICAL FILE VHDL PROGRAM: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity mux222 is Port ( a : in STD_LOGIC; b : in STD_LOGIC;s : in STD_LOGIC; z : out STD_LOGIC); end mux222; architecture Behavioral of mux222 is begin process(a,b,s) begin if(s='0')then z<=a; else z<=b; end if; end process; end Behavioral; RESULT: The 2:1 MULTIPLEXER has been successfully designed and implemented on XILINX SPARTAN KIT. VHDL PRACTICAL FILE EXPERIMENT NO. 10 AIM OF THE EXPERIMENT: To implement 4 bit binary to BCD converter using XILINX Software. THEORY: In computing and electronic systems, binary-coded decimal (BCD) (sometimes called natural binary-coded decimal, NBCD) is an encoding for decimal numbers in which each digit is represented by its own binary sequence. Its main virtue is that it allows easy conversion to decimal digits for printing or display and faster decimal calculations In BCD, a digit is usually represented by four bits which, in general, represent the values/digits/characters 0–9. Other bit combinations are sometimes used for a sign or other indications. VHDL PROGRAM: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity bcd is Port ( a : in STD_LOGIC_vector(3 downto 0); b : out STD_LOGIC_vector(7 downto 0)); end bcd; architecture Behavioral of bcd is begin VHDL PRACTICAL FILE process(a) begin case a is when "0000"=>b<="00000000"; When "0001"=>b<="00000001"; When "0010"=>b<="00000010"; When "0011"=>b<="00000011"; When "0100"=>b<="00000100"; When "0101"=>b<="00000101"; When "0110"=>b<="00000110"; When "0111"=>b<="00000111"; When "1000"=>b<="00001000"; When "1001"=>b<="00001001"; When "1010"=>b<="00010000"; When "1011"=>b<="00010001"; When "1100"=>b<="00010010"; When "1101"=>b<="00010011"; When "1110"=>b<="00010100"; When others=>b<="00010101"; End case; End process; End Behavioral; VHDL PRACTICAL FILE RESULT: The 4 bit binary to BCD convertor has been successfully designed and implemented on XILINX SPARTAN KIT. EXPERIMENT NO. 11 AIM OF THE EXPERIMENT: To implement 8 bit parity generator using XILINX Software. THEORY: Parity bits are extra signals which are added to a data word to enable error checking. There are two types of Parity - even and odd. An even parity generator will produce a logic 1 at its output if the data word contains an odd number of ones. If the data word contains an even number of ones then the output of the parity generator will be low. By concatenating the Parity bit to the data word, a word will be formed which always has an even number of ones i.e. has even parity. VHDL PROGRAM: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity parity is Port ( a : in STD_LOGIC_vector(7 downto 0); y : out STD_LOGIC); VHDL PRACTICAL FILE end parity; architecture Behavioral of parity is begin process(a) variable even : STD_LOGIC; begin even:='0'; for i in 7 downto 0 loop if a(i)='1' then even:= not even; end if; end loop; y<=even; end process; end Behavioral; RESULT: The 8 bit parity generator has been successfully designed and implemented on XILINX SPARTAN KIT. VHDL PRACTICAL FILE EXPERIMENT NO. 12 AIM OF THE EXPERIMENT: To implement 3:8 decoder using XILINX Software. THEORY: A decoder assumes the inputs x2x1x0 represent a 3-bit bitstring represented in UB. Thus, if x2x1x0 = 011, then the number 3 is input into the decoder, since 011 in UB has a value of 310. For each of the 8 possible inputs, exactly one of the outputs is set to 1. The rest have a value of 0. Thus, if x2x1x0 = 011, then z3 = 1 while all other outputs are 0. VHDL PRACTICAL FILE VHDL PROGRAM: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity decod is Port ( a : in STD_LOGIC_vector(2 downto 0); b : out STD_LOGIC_vector(7 downto 0)); end decod; architecture Behavioral of decod is begin process(a) begin case a is when "000"=>b<="00000001"; when "001"=>b<="00000010"; when "010"=>b<="00000100"; when "011"=>b<="00001000"; when "100"=>b<="00010000"; when "101"=>b<="00100000"; when "110"=>b<="01000000"; when others=>b<="10000000"; end case; end process; end Behavioral; VHDL PRACTICAL FILE RESULT: The 3:8 decoders has been successfully designed and implemented on XILINX SPARTAN KIT. EXPERIMENT NO. 13 AIM OF THE EXPERIMENT: To implement 2’s complementor for 8 bit binary number using XILINX Software. THEORY: A two's-complement system or two's-complement arithmetic is a system in which negative numbers are represented by the two's complement of the absolute value; this system is the most common method of representing signed integers on computers. In such a system, a number is negated (converted from positive to negative or vice versa) by computing its two's complement. An N-bit two's-complement numeral system can represent every integer in the range −2N-1 to +2N-1-1. VHDL PROGRAM: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity comple is Port ( a : in STD_LOGIC_vector(7 downto 0); b : out STD_LOGIC_vector(7 downto 0)); end comple; VHDL PRACTICAL FILE architecture Behavioral of comple is begin process(a) variable z: STD_LOGIC_vector(7 downto 0); variable y: STD_LOGIC_vector(7 downto 0); variable x: STD_LOGIC_vector(7 downto 0); begin z:="11111111"; y:="00000001"; x:=a xor z; b<=x + y; end process; end Behavioral; RESULT: The 2’s complementor for 8 bit binary number has been successfully designed and implemented on XILINX SPARTAN KIT. VHDL PRACTICAL FILE EXPERIMENT NO. 14 AIM OF THE EXPERIMENT: To implement 8:3 priority encoder using XILINX Software. THEORY: the operation of priority encoder is such that if two or more single bit inputs are at logic 1, then the input with highest priority will take precedence, and its particular coded value will be the output. VHDL PROGRAM: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity pri_en port (a:in unsigned (7 downto 0); valid: out std_logic; y: out unsigned (2 downto 0)); end pri_en; architecture behave of pri_en is begin VHDL PRACTICAL FILE process(a) begin valid<=’1’; if (a(7)=’1’) then y<=’111’; elsif (a(6)=’1’) then y<=’110’; elsif (a(5)=’1’) then y<=’101’; elsif (a(4)=’1’) then y<=’100’; elsif (a(3)=’1’) then y<=’ 011’; elsif (a(2)=’1’) then y<=’010’; elsif (a(1)=’1’) then y<=’001’; elsif (a(0)=’1’) then y<=’000’; else valid <=’0’; y<=’xxxx’; end if; end process; end behav; RESULT: The 8:3 priority encoders has been successfully designed and implemented on XILINX SPARTAN KIT. VHDL PRACTICAL FILE EXPERIMENT NO. 15 AIM OF THE EXPERIMENT: To implement 4 bit binary to grey code converter using XILINX Software. THEORY: a gray code is one in which adjacent numbers differ by one symbol. There are many gray codes en\even in binary. They can devise in any base. When grey is used without specifying which one, what is meant is reflected binary grey. To convert binary to grey, it is only necessary to XOR the original unsigned binary with a copy of itself that has been right shifted one place. VHDL PROGRAM: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity bin2grey is port (bin: in std_logic_vector (3 downto 0); grey : out std _logic_vector(3 downto 0)); end bin2grey; architecture exam of bin22grey is VHDL PRACTICAL FILE begin with bin select grey<= ‘0000’ when ‘0000’; ‘0001’when ‘0001’; ‘0011’when ‘0010’; ‘0010’when ‘0011’; ‘0110’when ‘0100’; ‘0111’when ‘0101’; ‘0101’when ‘0110’; ‘0100’when ‘0111’; ‘1100’when ‘1000’; ‘1101’when ‘1001’; ‘1111’when ‘1010’; ‘1110’when ‘1011’; ’1010’when ‘1100’; ‘1011’when ‘1101’; ‘1001’when ‘1110’; ‘1000’when others; end exam; RESULT: The 4 bit binary to grey code converter has been successfully designed and implemented on XILINX SPARTAN KIT.