Quiz 6 CDA 3101 (Introduction to Computer Organization) by moti

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									                                      Arizona State University
                            Computer Science and Engineering Department


                            CSE 422: Microprocessor System Design II
                                          Fall 2003
                                         Midterm Exam

Date: October 13, 2003                                                  Time: 10:40 – 11:30 am
Instructor: Dr. Hasan Çam

Student Name:
Student ID:


   Note: The last question is a take-home programming exercise. As stated in the midterm exam slides
   posted on the class website, the hard copy of the solution is due the lecture on Friday, 17 Oct 2003,
   and the soft copy of the VHDL code with all files and directories should be emailed to the TA by
   5pm on Friday, 17 October 2003.


                          Question 1      (20 points)

                          Question 2      (25 points)

                          Question 3      (25 points)

                          Question 4      (30 points)

                                     Total



   1. The exam is open book and open notes.
   2. Show all your work.
   3. Without proper justification and details of steps, correct answers alone may not carry full credit.
      Your answers must be concise and may lose points if your answers include incorrect or
      irrelevant statements.
   4. If you feel it is necessary to have additional assumptions, state clearly the assumptions and
      proceed to answer the questions.




                                                   1
1. (20 points)
    Using the following code, answer questions (a) and (b) by filling in the blanks with appropriate
    values.
          type opcode is (nop, load, store, add, subtract, negate, branch, halt);
          subtype arith_op is opcode range add to negate;

(a; 2pts) arith_op’base’left = ___________

(b; 2pts) arith_op’base’succ(negate)=___________

    Using the following code, answer questions (c) to (e) by filling in the blanks with appropriate
    values.
          type level is (off, standby, active1, active2);

(c; 2pts) level’pos(standby) = ___________

(d; 2pts) level’val(2) = ___________

(e; 2pts) level’succ(active2) = ___________

     As for question (f), write an assertion statement that expresses the requirement that packet
     length is greater than zero. The assertion statement should have a report clause indicating the
     reception of an empty packet, along with a severity clause of warning.
(f; 2pts) assert _______________________________
         report ________________________
         severity ________________________

    As for question (g), write an equivalent concurrent signal assignment for the following process
    statement.
        PC_incr: process is
        begin
           next_PC <= PC + 4 after 5ns;
           wait on PC;
        end process PC_incr;

(g; 2pts) PC_incr: ____________________________________________

    Using the following code, answer questions (h) to (j) by filling in the blanks with True or False.

          constant data: bit_vector(31 downto 0) ;

(h; 2pts) _________       data(4 downto 1) = “0000”;

(i; 2pts) _________       data(5 downto 10)is a slice of 5 elements of data.

(j; 2pts) _________       data(30 to 31) is equivalent to data(31 downto 30).

2. (25 points) Given the following VHDL code, fill in the entries of the table.


                                                    2
library ieee;
use ieee.std_logic_1164.all;

entity box is
        port (cond: inout std_logic);
end box;

architecture exam of box is
        signal clk, result: std_logic :='0';
begin
        clk <= '1' after 5 ns, '0' after 15 ns, '1' after 35 ns;

       A : process (clk)
        begin
                if ( clk = '1' ) and ( clk'event ) then
                         result <= not result;
                end if;
        end process A;

       B : cond <= result when clk='0';
end exam;

            Time instance                  clk            result   cond
                    0                                               U
                0+delta
                    5
                5+delta
                   15
                15+delta
                   35
                35+delta




                                             3
3. (25 points) Write down a VHDL structural model code for an eight-bit edge-triggered register using
   the following behavioral model of an edge-triggered flip-flop. The structural model should include
   the entity declaration and a structural architecture body.


  entity edge_triggered_exam is
    port ( clk, clr, D : in bit;
           Q : out bit);
  end entity edge_triggered_exam;

   architecture behavioral of edge_triggered_exam is
   begin
      state_change : process (clk, clr) is
      begin
           if clr = `1’ then
                 Q <= `0’ after 2 ns;
           elsif clk’event and clk = `1’ then
                 Q <= D after 2 ns;
           end if;
      end process state_change
  end architecture behavioral;




                                                 4
5
4. (30 points) The following question is a take-home exercise as stated on the first page of this exam
   paper. (This question is the same as Exercise 5.29 from the textbook).

Develop a behavioral model for a D-latch with tristate output. The entity declaration is

        entity d_latch is
                port (latch_en, out_en, d : in std_ulogic;   q : out std_ulogic);
        end entity d_latch;

When latch_en is asserted, data from the d input enters the latch. When latch_en is negated,
the latch maintains the stored value. When out_en is asserted, data passes through to the output.
When out_en is negated, the output has the value `Z’ (high-impedance). The propagation delay
from latch_en to q is 3 ns and from d to q is 4 ns. The delay from out_en asserted to q active
is 2 ns and from out_en negated to q high-impedance is 5ns.




                                                    6

								
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