Get documents about "PCB Layout Considerations
Document Sample
Homework 6: Printed Circuit Board Layout Design
Due: Thursday, October 6
Team Code Name: V.A.V.A. GPS DATA LOGGER Group No. 4
Team Member Completing This Homework: Akhil Dharwadkar
NOTE: This is the third in a series of four “design component” homework assignments, each
of which is to be completed by one team member. The completed homework will count for
10% of the team member’s individual grade.
Report Outline:
Introduction (brief description of design project, with a focus on layout
considerations)
PCB layout design considerations (describe the special considerations you took
into account when designing the PCB layout, including signal routing, trace
sizing, EMI reduction, etc.)
Documentation for PCB layout design
o Updated OrCAD schematic (printed on 11x17 paper)
o Updated OrCAD design rule check report
o Updated OrCAD bill of materials report
o Updated OrCAD routing statistics report
o Top and bottom copper (printed in color)
List of References (at minimum, Motorola AN1259)
Evaluation:
Component/Criterion Score Multiplier Points
Introduction & Layout
0 1 2 3 4 5 6 7 8 9 10 X3
Considerations
Documentation for PCB Layout
0 1 2 3 4 5 6 7 8 9 10 X5
Design
List of References 0 1 2 3 4 5 6 7 8 9 10 X1
Technical Writing Style 0 1 2 3 4 5 6 7 8 9 10 X1
TOTAL
Introduction
The V.A.V.A GPS Data Logger is a data logging device that
logs information like latitudinal and longitudinal (GPS) coordinates, velocity, etc of a
vehicle. The device displays this information to the driver of the vehicle on a LCD which
is mounted on the dashboard. This device also hosts an embedded web server so that the
logged data can be synchronized with a PC using a web interface. An example of this
application would be a car rental company using this device as a fleet management
system for their vehicles. This device consists of two parts – the data logging unit (GPS
Unit) that sits in the trunk of the vehicle and the display unit (LCD Unit) which is
mounted on the dashboard.
Many PCB layout techniques have been taken into consideration while designing
the PCB layout. Special Emphasis has been laid on reducing EMI; signal routing, trace
width, footprint designs and board-size constraints. Standard PCB layout procedures such
as grounding unused general purpose I/O pins and routing wires at 45 degree turns to
reduce transmission reflection have also been implemented.
PCB Layout Considerations
Since EMI can be the main cause of problems in a circuit, special focus was given
into EMI reduction. Following techniques have been applied to considerably reduce EMI
in our layout:
• Clever component placement techiniques1 have been used to reduce noise
coupling. The analog components such as the RF transmitter2 and the RF
receiver3 are placed far apart from all the digital components as well as the
high current components like the battery chargers4 and DC-DC regulators5.
• Effective grounding techniques1 have been used as most EMI problems can be
resolved using efficient grounding methods. The most effective way of
reducing total power and ground inductance is to run the signal and the return
paths very close together. We have exploited the above theory by running the
power and ground rails with approximately identical geometry on opposite
sides of the board. Also, star-point grounding was used as a local sub
grounding point (wherever required) on the layout.
• IC decoupling capacitors1 have been used to remove the unwanted glitches
which occur due to fast switching logic gates. These decoupling capacitors
have been places very close to all the IC’s so that they can provide
instantaneous charge. Bulk capacitors1 have also been used so as to recharge
these decoupling capacitors. We have used a 470uf bulk capacitor which
should be good enough to recharge all the decoupling capacitors.
• CMOS inputs/outputs have very high impedance and consequently can float to
any voltage if unconnected6, and this voltage could be within a threshold
switchover region of the gate. To prevent this, all the unused general purpose
inputs/outputs micro-controller pins have been grounded via a 10 KΩ resistor.
• Instead of 90 degree turns, 45 or 135 degree turns have been used at all
required points to decrease transmission reflections.
Board-size was one of the major constraints for us while designing the layout.
Since we have two boards, we had to make sure that both occupied a combined area of
less that 60 square inches7. Moreover, since only one board is fabricated for free7, we had
to design both the layouts on a single piece as of now. Once we get the fabricated board,
we will cut it into two parts – the GPS unit and the LCD unit. These two designs are
completely independent of each other and cutting the board into two parts will not affect
the functionality of the either design.
Regarding trace widths and signal routing, we used an online PCB trace width
calculator8 to find appropriate trace widths for our layout. The calculated trace width for
the power and ground signals was approximately 44 mils, but we ceiled up that value to
50 mils. For all the other signals, we used a width of 12 mils. It was impossible for us to
route all the signals on one layer. Therefore, we used two layers for routing all the
signals. We used 139 Via connectors to switch between the top layer and the bottom
layer.
Finally, other items that had to be taken into consideration were the footprints and
placement of components like DC power jack9, reset buttons10, GPS receiver11 and the
RCM 330012 micro-controller module. We more or less made the footprints of all our
components just to make sure that we don’t run into problems when it comes to soldering
all components on the PCB. Also, we made sure that DC power jack and the reset buttons
are mounted at one corner of the PCB so that they are easily accessible to the user, the
GPS receiver is mounted in such and a way that the GPS antenna comes out from one
corner of the PCB and finally, the RCM 3300 micro-controller is mounted in such a way
that the RJ-45 Ethernet jack faces outwards.
Documentation for PCB layout design (see attached documents)
o Updated OrCAD schematic
o Updated OrCAD design rule check report
o Updated OrCAD bill of materials report
o Updated OrCAD routing statistics report
o Top and bottom copper (printed in color)
References
[1] Motorola AN1259
http://shay.ecn.purdue.edu/~dsml/ece477/Homework/Fall2005/index.html
[2] RF Transmitter - TXM-315-LC-ND RF
http://www.linxtechnologies.com/images/products_cat/rf_modules/lc_series/lc-
txm_manual.pdf
[3] RF Transmitter - RXM-315-LC-S-ND RF
http://www.linxtechnologies.com/images/products_cat/rf_modules/lc_series/lc-s-
rxm_manual.pdf
[4] Battery Charger - MAX713
http://pdfserv.maxim-ic.com/en/ds/MAX712-MAX713.pdf
[5] DC-DC regulators - MAX738A and MAX1831
http://pdfserv.maxim-ic.com/en/ds/MAX730A-MAX744A.pdf
http://pdfserv.maxim-ic.com/en/ds/MAX1830-MAX1831.pdf
[6] The Circuit Designer’s Companion, Author - Tim Williams
ISBN: 0 7506 6370 7
[7] The ECE department fabricates one PCB having an area less than 60 square inches.
One board is printed free of cost.
[8] PCB Trace Width Calculator
http://www.geocities.com/CapeCanaveral/Lab/9643/TraceWidth.htm
[9] DC Power Jack - PJ-102B
http://www.cui.com/pdffiles/PJ-102B.pdf
[10] Reset Buttons – SW401-ND
http://rocky.digikey.com/WebLib/Omron%20Web%20Data/B3F.pdf
[11] GPS Receiver - Lassen LP, Trimble
http://trl.trimble.com/dscgi/ds.py/Get/File-4753
[12] Rabbit Micro-controller – RCM3300
http://www.rabbitsemiconductor.com/products/rcm3300/rcm3300.pdf
GND RCM Header 1 GND GND RCM Header 2 GND Debug Header 1 Debug Header 2
STATUS 2 1 GND R41 10K 2 1 STATUS 2 1 2 1
R22 10K 4 3 10K R21 R43 10K 4 3 10K R42 4 3 4 3
R24 10K 6 5 10K R23 R45 10K 6 5 10K R44 6 5 6 5
R26 10K 8 7 10K R25 R47 10K 8 7 10K R46 8 7 8 7
R28 10K 10 9 10K R27 R49 10K 10 9 10K R48 10 9 10 9
CS 12 11 WP R51 10K 12 11 10K R50 CS 12 11 WP 12 11
R29 10K 14 13 SCLK R53 10K 14 13 10K R52 14 13 SCLK 14 13
SI 16 15 SO R55 10K 16 15 10K R54 SI 16 15 SO 16 15
RXD1 18 17 TXD1 R57 10K 18 17 10K R56 RXD1 18 17 TXD1 18 17
20 19 R59 10K 20 19 10K R58 20 19 20 19
22 21 R61 10K 22 21 10K R60 22 21 22 21
R31 10K 24 23 10K R30 24 23 10K R62 24 23 24 23
R32 10K 26 25 TX_DATA 26 25 26 25 TX_DATA 26 25
R34 10K 28 27 10K R33 RST 28 27 28 27 RST 28 27
R36 10K 30 29 10K R35 30 29 30 29 30 29
R38 10K 32 31 10K R37 GND 32 31 VCC_3 32 31 32 31
R40 10K 34 33 10K R39 GND 34 33 34 33 34 33
RCM3300 RCM3300 RCM3300 RCM3300
Atmel 8Mb Flash VCC_3
RF Transmitter VCC_3 AT45D081/SOIC
R7 SI 6 7 SO GROUND Prime_Power 2 1
GND GND 10 SI SO TXD1
1 GND1 GND8 8 4 3
TX_DATA 2 7 C19 SCLK 5 23 VCC_3 GND 6 5 RXD1
GND DATA VCC GND 10uF SCLK RDY/BUSY GND
3 GND3 GND6 6 8 7
GND 4 5 ANT2 RST 24 28 GND
LADJ ANT GND WP RST VCC
25 WP
CS 4 1 GND C35 GPS
CS GND 10u GPS Header
(from Car Battery)
VCC_12 2N6109 Q2
R16 R17
1.4k C30 150
0.01u
D5 R20
6 14 1N4001 10 8
TLO DRV FB VCC_3
5 THI 2 IN LX 1
C20 2 4 3 L3
BATT+ (4.8 V) IN LX 2.2u C31
11 CC BATT- 12 12 VCC LX 16
C29 16 PACK+ C34 GND 9 14 120u
10u 0.01u REF 470p GND LX
FASTCHG 8 5 nSHDN PGND 13
3 6 15 GND
R18 PGM0 COMP PGND
4 PGM1 7 TOFF FBSEL 11
68K 9 10 GND
PGM2 PACK- C33 R19 REF
10 PGM3 C28 2.2u 39k C32
7 10u 1u
TEMP GND MAX738/SO
1 VLIMIT
13 Step Down Regulator
GND Rsense2
15 V+
0.38
R14 C27 MAX713/S0
22k 1u Battery Charger GND
GND
J5 3.6V DC -3.6V DC VCC_12 1 J10
SW2 PACK+ 2 1 PACK- C37 2 Title
VCC_3 1 2 RST ANT2 1 470u 3 477 Group 4 - VAVA - GPS Schematic
Reset SPST Size Document Number Rev
CON1 J11 HEADER 1x2 GND CONN PWR 3-P 1
Date: Monday, October 10, 2005 Sheet 1 of 1
J12 HEADER 9X2 GND2 RF Reciever
GND2 RXM-315-LC-S J8 J9
LCD_DATA1 18
SPI_CLK 2 17 R69 ANT 16 1 0.6V DC -0.6V DC 3.6V DC -3.6V DC
R63 HBQ 10K VCC_5 GND2 ANT NC GND2 BAT+ 2 BAT- PACK+ 2 PACK-
3 16 15 GND NC 2 1 1
10K RST2 4 15 R68 14 3 R6
C18 NC NC
GND2 5 14 10K 13 4 GND2 200 C12
SPI_BUSY 6 R67 GND2 NC GND
13 12 NC VCC 5 10u
nSPI_CS 7 12 R66 10K 11 6 VCC_5 HEADER 1x2 HEADER 1x2
TOGGLE 8 10K R65 NC PDN VCC_5
11 10u 10 NC NC 7
R64 9 10 RS232 10K 9 8 RF_DATA
10K NC DATA
GROUND RF_DATA 2 5 RS232
GND2 T1IN T1OUT
1 T2IN T2OUT 18
GND2 VCC_12_2 1 J7 GND2
C14 2 GND2 4 3
0.01u C36 GND2 19 R1IN R1OUT
3 R2IN R2OUT 20
GND2 Fuel Gauge BAT- GND2 470u
BQ26231 R10 13 VCC_5
C13 GND2 100k R13 CONN PWR 3-P C1+
14 C1- VCC 7
0.1u 1 8 C15 0.02 12 GND2
BAT+ NC NC 0.01u C2+
2 VCC SR1 7 11 C2-
GND2 3 6 PACK- J6 15 C17
HBQ VSS SR2 R11 C2+ 1u
4 HBQ RBI 5 16 C2-
R9 R8 100k Toggle SPST SW1 1 8 GND2
100 D3 100 VCC_5 VCC_5 TOGGLE_IN V+ GND 6 GND2
1 2 10 V- GND 9
5.6V C16 D4 R12 17
(500mW) 0.1u 1N914 1M CON1 V-
GND2 GND2 Reset SPST SW3 ANT RS232 Translator
VCC_5 1 2 RST2_IN MAX233A/DIP
(from Car Battery) GND2
VCC_12_2 2N6109 Q1
C6
R1 R2 0.01u C10
1.4k C3 150 330p U4 VCC_5
0.01u
D1 8 12 L2
CC LX
6 TLO DRV 14 1N4001 3 REF LX 13
5 7 14 33u
C4 THI R5 SS LX C11
BATT+ 2
11 12 (7.2 V) 510K C7 9 D2 100u
C1 CC BATT- PACK+ 0.1u OUT
16 REF 2 SHDN 1N5817
10u 0.01u 8 GND2
FASTCHG GND2 GND2
3 PGM0 1 V+
R3 4 15
68K PGM1 V+
9 PGM2 16 V+
10 PACK-
PGM3 C5 C8 C9 16x2 LCD
7 10u 68u 1u Step-Down Regulator
MAX738/SO SKD162-632
TEMP
1 VLIMIT
13 GND2 1 GND2
GND Rsense1 VCC_5
15 V+ 2
0.52 3 VCC_5
R4 C2 MAX713/S0 4 LCD_DATA
22k 1u Battery Charger GND2 J13 5 nSPI_CS
TOGGLE_IN 1 6 TOGGLE 6 SPI_CLK
GND2 2 5 VCC_5 7 SPI_BUSY
RST2_IN 3 4 RST2
GND2 MAX-6817 Debouncer
N:\ee477\combined_project.DRC
1:
2: Checking Pins and Pin Connections
3:
4: --------------------------------------------------
5: Checking Schematic: SCHEMATIC1
6: --------------------------------------------------
7: Checking Electrical Rules
8:
9: Checking for Unconnected Nets
10:
11: Checking for Invalid References
12:
13: Checking for Duplicate References
14:
15: Check Bus width mismatch
16:
1
N:\ee477\Combine_Project.BOM
1: 477 Group 4 - VAVA - GPS Schematic Revised: Monday, October 10, 2005
2: Revision: 1
3:
4:
5:
6:
7:
8:
9:
10: Bill Of Materials October 10,2005 4:48:39 Page1
11:
12: Item Quantity Reference Part
13: ______________________________________________
14:
15: 1 3 U2,U11,BQ26231 TXM-LC
16: 2 7 C1,C5,C12,C18,C28,C29, 10u
17: C35
18: 3 5 C2,C9,C17,C27,C32 1u
19: 4 7 C3,C4,C6,C14,C15,C20,C30 0.01u
20: 5 3 C7,C13,C16 0.1u
21: 6 1 C8 68u
22: 7 1 C10 330p
23: 8 1 C11 100u
24: 9 1 C19 10uF
25: 10 1 C31 120u
26: 11 2 L3,C33 2.2u
27: 12 1 C34 470p
28: 13 2 C36,C37 470u
29: 14 2 D1,D5 1N4001
30: 15 1 D2 1N5817
31: 16 1 D3 5.6V
32: 17 1 D4 1N914
33: 18 2 J5,J6 CON1
34: 19 2 J7,J10 CONN PWR 3-P
35: 20 3 J8,J9,J11 HEADER 1x2
36: 21 1 J12 HEADER 9X2
37: 22 1 J13 MAX-6817 Debouncer
38: 23 1 L2 33u
39: 24 2 Q1,Q2 2N6109
40: 25 1 Rsense1 0.52
41: 26 1 Rsense2 0.38
42: 27 2 R1,R16 1.4k
43: 28 2 R2,R17 150
44: 29 2 R3,R18 68K
45: 30 2 R4,R14 22k
46: 31 1 R5 510K
47: 32 1 R6 200
48: 33 2 R7,R20 10
49: 34 2 R8,R9 100
50: 35 2 R10,R11 100k
51: 36 1 R12 1M
52: 37 1 R13 0.02
53: 38 1 R19 39k
54: 39 49 R21,R22,R23,R24,R25,R26, 10K
55: R27,R28,R29,R30,R31,R32,
56: R33,R34,R35,R36,R37,R38,
57: R39,R40,R41,R42,R43,R44,
58: R45,R46,R47,R48,R49,R50,
59: R51,R52,R53,R54,R55,R56,
60: R57,R58,R59,R60,R61,R62,
61: R63,R64,R65,R66,R67,R68,
62: R69
63: 40 1 SKD162-632 LCD
64: 41 3 SW1,SW2,SW3 SW KEY-SPST
1
N:\ee477\Combine_Project.BOM
65: 42 1 U3 MAX233A/DIP
66: 43 2 U4,U14 MAX738/SO
67: 44 2 U5,U13 MAX713/S0
68: 45 4 U6,U7,U8,U9 RCM3300
69: 46 1 U10 GPS
70: 47 1 U12 AT45D081/SOIC
71:
2
STATS
*****************************
* *
* STATISTICS REPORT *
* *
* N:\PCB\TEMP2.MAX *
* Mon Oct 10 03:59:24 2005 *
* *
*****************************
STATISTIC ENABLED TOTAL
---------------------------------------------------------------------
Board Area 59.4 59.4
Equivalent IC's 37.9 37.9
Sq. inches per IC 1.57 1.57
# of pins 569 569
Layers 4 28
Design Rule Errors 0 0
Time Used 15:25 15:25
% Placed 100.00% 100.00%
Placed 137 137
Off board 0 0
Unplaced 0 0
Clustered 0 0
Routed 350 350
% Routed 98.87% 98.87%
Unrouted 0 0
% Unrouted 0.00% 0.00%
Partials 4 4
% Partials 1.13% 1.13%
Vias 139 139
Test Points 0 0
Vias per Conn 0.39 0.39
Segments 1524 1524
Page 1
STATS
Connections 354 354
Nets 114 114
Components 137 137
Footprints 191 191
Padstacks 41 41
Obstacles 684 684
Theoretical Dist 345.7 345.7
Routed Dist 323.5 323.5
Unrouted Dist 29.3 29.3
Page 2
Related docs
