New conﬁgurations for the three-phase
asymmetrical multilevel inverter
S. Mariethoz, A. Rufer
EPFL - LEI
phone : (+41) 21 6935623
fax : (+41) 21 6932600
Abstract— This paper deals with cascade multilevel inverters. It B. Asymmetrical multilevel inverter basic principles
focuses on asymmetrical topologies where the cell input voltages
The cascade multilevel inverter consists of a set of series
are of different values. These hybrid topologies might be used in
several applications. Nevertheless, the need of DC-DC converters connected cells. An asymmetrical multilevel inverter is deﬁned
to supply the cells of reversible multilevel converters increases the by its topology, i.e. the set of combined cells, and by the
cost and losses of such inverters. It limits their application ﬁeld. conﬁguration of their input voltages. One important feature
Furthermore, the simultaneous-commutation problem, which in- is that the cells have to be insulated one from each other, this
creases the switching losses for some operating points, reduces the
constitutes the major drawback of these structures.
design choice to conﬁgurations of lower resolution. Combining
in series a 3-phase 6-switch voltage source inverter with single Four-switch H-bridge voltage source inverters might be
phase H-bridges, we obtain an asymmetrical hybrid cascaded chosen for the cells and they can be supplied by bidirectionnal
multilevel inverter with advantageous properties in terms of DC-DC converters as shown in Fig. 1(a).
voltage resolution and energetic efﬁciency. This paper describes 1) Possible beneﬁts of the hybridation: Due to the different
the design and use of such a structure, the way to increase the input voltages of the cells, high-voltage switches presenting
asymmetrical multilevel inverters resolution.
low relative conduction losses are combined with low-voltage
switches having low commutation time. Naturally, for most
I. I NTRODUCTION operating points, the switching frequency of low voltage cells
is higher. Together with the switch characteristics, one can take
A. Multilevel inverters advantage of this speciﬁcity. For applications which need a low
The multilevel inverter was introduced as a solution to switching frequency, the conduction losses are predominant
increase the converter operating voltage above the voltage and the hybrid inverter has higher losses than a conventional
limits of classical semiconductors. There are several ways to inverter, but above a given frequency it would theoretically
build multilevel inverters. The main topologies are the neutral allow lower losses.
point clamped inverters , the ﬂying capacitors inverters From the voltage resolution point of view, with the same
 and the cascade inverters . This paper investigates the number of cells, the asymmetrical multilevel inverter allows a
latter inverters and focuses on topologies where the input higher resolution than symmetrical multilevel inverters. In the
voltage values are different . These topologies are known symmetrical case, the number of levels grows proportionally
as asymmetrical or hybrid multilevel inverters, they may be to the number of cells, in the asymmetrical case, it grows
divided in three categories by ascending order of hybridation: exponentially.
2) Supply issue: The main drawback of the cascade inverter
• several inverters are series connected, all with the same is the need of insulated supplies. It increases the converter
topology but at least one with a different input voltage complexity (and cost) and reduces the energetic efﬁciency.
, , , For some asymmetrical conﬁgurations, some levels can only
• several inverters are series connected, with different be generated by summing contributions of opposite signs.
topologies and different input voltages , , , , When generating such levels, the power is ﬂowing from the
• several converters of different nature, with different DC supply to the load for some cells and from the load to
topologies and input voltages are series connected. In , the DC supply for the others. As a consequence, for many
a H-bridge inverter is combined with a linear ampliﬁer operating points, in addition to the effective load power, there
to get a quasi-linear ampliﬁer, with a high-energetic is a circulation of power between the cells which increases
efﬁciency, high relatively to linear ampliﬁers. dramatically the inverter losses. The beneﬁt of the hybridation
The way the cells can be associated is common for all these is wasted by these additional losses.
asymmetrical topologies. This paper reviews and completes the Furthermore, the average circulation of power doesn’t nat-
cell association rules. urally cancel over a whole period. For some conﬁgurations
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and/or applications, it can be balanced. If it cannot, the supply
must be bidirectional even if the load isn’t. In  a solution U i,1 U O ,1
to the supply issue has been presented. The low-voltage cell
supplied are saved and the converter energetic efﬁciency is
3) Simultaneous commutation issue: For some conﬁgura-
tions and for some operating points (the same as for the sup-
ply issue), there are many simultaneous commutations which
increase the switching losses. By following adequate design
(a) basic cascade inverter scheme for one phase
rules and control strategy, this problem can be avoided .
So far, the conﬁgurations with the highest voltage-resolution ∆U1 ∆U2 ∆U3 N Nsv prop.
were not considered as suitable to get a PWM output. 1 2 − 7 127 m
Our goal is to get a bidirectional converter with high voltage- 1 3 − 9 217 u, vm
1 1 4 13 469 m
resolution and high energetic-efﬁciency. For that purpose, we
1 1 5 15 631 u, vm
work on the optimization of the converter structure and on the 1 2 6 19 1027 m
cell association rules. 1 3 9 27 2107 u, vm
(b) several state-of-the-art conﬁgurations
II. I NVESTIGATED INVERTER STRUCTURE
∆U1 ∆U2 ∆U3 N Nsv prop.
A. Inverter structure principles
1 4 − 9 319 vu
From the power circulation point of view, the 3-phase 6- 1 1 6 15 805 vm
switch voltage source inverter is an advantageous structure 1 1 7 15 991 vu
because the DC-side is shared by the 3 phases. One draw- (c) several new conﬁgurations
back of this simple structure is that it generates only two
Fig. 1. (a) Basic multilevel inverter structure for one phase, (b) some of
levels. Considering the resolution and the switching losses, its state-of-the-art conﬁgurations, (c) some of the new possible conﬁgurations
the cascade multilevel inverter is a more appropriate structure, when used in a three-phase application. In the tables, ∆Ui are the steps of the
but to get a reversible converter, its cells have to be fed by cells, N the number of levels of the resulting inverter, Nsv the number of space
vectors. The column prop. lists the conﬁguration properties : u uniformity; m
reversible DC-DC converters as shown in Fig. 1(a). It implies levels usable for modulation; vu uniform space vectors; vm space vectors
a triple conversion for a simple DC/AC converter, what is not usable for modulation (m ⇒ u, vm ⇒ vu). Compare with the improved
compatible with a high energetic-efﬁciency. structure in Fig. 2.
Combining both structures, we get an asymmetrical mul-
tilevel inverter as shown in Fig. 2(a). Compared to another
reversible cascade inverter, this structure still has DC-DC
converters, but depending on the conﬁguration design, only Taking into account the speciﬁcities of the inverter, there are
a fraction — from 20% to 50% — of the power goes through several possible optimizations.
them. The smallest part of the power goes through 3 secondary
AC/DC converters and the largest part of the power is directly Instead of using as many transformers as DC-DC converters,
converted by the 6-switch large inverter. An example of the only one with multiple secondaries may be used. In this way,
power repartition is shown in Fig. 3. the primary DC-AC converter supply the total power of the
A similar structure has already been presented in  with a low-voltage cells, it doesn’t see and thus doesn’t have to supply
symmetrical supply. In this case, only four levels are generated the power circulation between them. It allows a small reduction
and the power repartition is not favourable: only a small part of the converter losses.
of the power is processed by the 3-phase H-bridge.
The switching frequency must be the same for the primary
The 3-phase H-bridge inverter might be replaced by any
and for the secondary converters. As a consequence, the best
other 3-phase cell. In  it is substituted by a N.P.C. inverter.
is to have the same devices for all converters. For that purpose,
The beneﬁt of this structure is the same as for the proposed
as many primary DC/AC modules as necessary might be series
structure, with twice the voltage ratings and a higher resolution
connected. In that way, we avoid to use devices with different
for the same number of series connected H-bridges. The
switching characteristics for the primary and secondaries.
choice of the adequate 3-phase cell structure should mainly
be determined both by the application voltage ratings and by For some applications, the feeding of the low-voltage cells
the available devices. The resolution can be adjusted afterward of the hybrid multilevel inverter could be omitted, at the
by the number of series connected H-bridges. price of a smaller output voltage range for the same devices.
The resulting structure is simpler, but the control is quite
B. Cell supply complex. A detailed analysis of the control of such a structure
The fraction of power that is processed by the low-voltage is presented in ,  for an hybrid combination of a N.P.C
cells still provokes an important part of the converter losses. inverter with H-bridge ﬁlter cells.
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c e ll s u p p ly
U O ,1
U i,1 0
U O ,2
0 0.2 0.4 0.6 0.8 1
(a) effective power
U i,1 1.5
U O ,3
L .V .
U i= U i,2 0.5
H .V .
(a) 3-phase efﬁciency improved inverter scheme 1
∆U1 ∆U2 ∆U3 N Nsv prop. tot
1 2 − 5 61 m 0 0.2 0.4 0.6 0.8 1
1 3 − 6 91 u + vm (b) apparent power
1 4 − − 121 vu
1 1 4 9 217 m Fig. 3. Power distribution function of the magnitude for a sine reference,
for the proposed topology with a ratio of 3 between the input voltages. +
1 1 5 10 271 u + vm high-voltage cell, × low voltage cell, ∗ total.
1 1 6 − 325 vm
1 1 7 − 379 vu
1 2 6 13 469 m
1 3 9 18 919 u
1 3 13 − 1327 vu
(b) several conﬁgurations k
∆Uk ≤ ∆Uk+1 ≤ (nj − 1) · ∆Uj (2)
Fig. 2. (a) Improved 3-phase multilevel inverter structure and its associated
possible conﬁgurations. Compare with the basic structure in Fig. 1, see Fig. j=1
1 legend for the symbol deﬁnitions.
Several possible conﬁguration are listed in Fig. 1(b) and 2(b)
according to these two rules.
III. S TATE - OF - THE - ART CONFIGURATIONS
IV. N EW CONFIGURATIONS
Two and three are the mostly used ratios between the suc-
A. 3-phase conﬁgurations for low switching losses and high
cessive input voltages of the asymmetrical multilevel inverter
cells. The other possible conﬁgurations of the single-phase
inverters are described in , we summarize these results To keep the high-voltage cell switching frequency close to
in the following. To obtain a structure that generates uniform the fundamental frequency in previous works , , ,
levels, the supply voltages must fulﬁll the uniformity condition: the possible designs for a PWM inverter have been limited to
those observing the modulation condition (2). These limitations
are based on the single-phase case analysis. It is obvious
∆Uk ≤ ∆Uk+1 ≤ ∆U1 + (nj − 1) · ∆Uj (1)
that every solution observing (2) has the same properties for
3-phase inverters. In this section, we examine those which
where ∆Uk and nk are the step and number of levels of aren’t, and we will show that more conﬁgurations with higher
the k th cell and where ∆U1 is also the step of the resulting resolutions are available for 3-phase inverters.
inverter. The conﬁgurations fulﬁlling (1) work well to generate 1) Proposed inverter PWM ratings: Considered as a single
a step stair output, but they are ill-suited for a modulated one. phase structure, the proposed inverter is made of one two-
Switches of different blocking voltages are used to build an level inverter connected in series with several 3-level H-bridges
asymmetrical multilevel inverter. So far, switches with high connected in series. Let’s examine the proposed structure
blocking capabilities have smaller commutation capabilities. To when it has one 3-level H-bridge per phase. Following the
minimize the number of commutations of high-voltage cells, modulation condition (2), the maximum input voltage ratio is
the inverter input voltages has to be designed according to the 2. With this ratio, ﬁve levels can be generated as shown in
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Fig. 4(a). One can verify that any pair of adjacent levels can
be modulated by moving along the low voltage cell axis.
1 0 2 1 −0.5 2.5
Following the uniformity condition (1), the maximum input
voltage ratio is 3, then 6 uniform levels are generated as shown
0 −1 1 0 −1.5 1.5
in Fig. 4(b). The pair −0.5, 0.5 cannot be modulated without
switching the high-voltage cell. Let’s examine the modulation
−1 −2 0 −1 −2.5 0.5
−1 0 1 −1.5 0 1.5 process for this conﬁguration considering the 3-phase structure.
The high-voltage cell generates 7 space vectors. The H-bridge
(a) ratio 2 (b) ratio 3 inverters of the same input voltages are put together to form a
1 −1 3 3-phase cells. When their 3 negative output terminals are tied
together, these cells generate 19 space vectors in the α − β
0 −2 2 plane. For a combination of two cells, Fig. 5(a) shows the 7
space vectors generated by the high-voltage cell and the 19
−1 −3 1
−2 0 2
ones generated by the low-voltage one when the cell input-
voltage ratio is 3. Combining these two sets of space vectors,
(c) ratio 4 91 multilevel inverter space vectors are obtained. They are
Fig. 4. State-space representation of the level generated for the proposed shown in Fig. 5(b). Some of these space vectors overlap, if
structure with one H-bridge in series for different voltage ratios. they don’t, there were 133.
To modulate a space-vector reference, the 3 adjacent space
vectors forming a triangle around it are modulated as described
in : all possible modulation triangles are shown in Fig. 5(c).
Combined with the 19 space vectors of a low-voltage cell,
each high-voltage cell space vector — base vector — produces
19 space vectors regularly disposed over an hexagonal area,
ﬁlled in light grey in Fig. 5(e). These 19 space vectors might
be generated successively keeping the same base space vector,
i.e. the same high-voltage cell space vector. Hence, when the
three adjacent space vectors to modulate belong to the same
hexagonal area, they can be generated with the same base
high voltage cell space vector. Consequently, any reference trajectory moving
low voltage cell
inside one of these seven 19-space-vectors hexagons may be
(a) cell space vectors (b) space vector combinations followed without switching the high-voltage cell. Following
any reference, the high-voltage cell has to be only switched
when moving out of an hexagonal area. In this latter case, the
base vector has to be changed. Since most of the area reachable
by the inverter is covered by the hexagonal areas as ﬁlled in
light grey in Fig. 5(d), for most of the trajectories, the high-
voltage cell would switch at a frequency close to the funda-
mental frequency. For instance, following a circular reference
in the α−β plan, three 120◦ dephased sine references, the high
voltage cell has to be switched each time an hexagon is left
(c) modulation triangles (d) modulation domain
for another. The base vector will not be changed more than 6
times a period. Although this conﬁguration doesn’t fulﬁll the
single-phase modulation condition (2), it seems working well.
2) The modulation domain: the concepts contained in this
example can be expressed with a few deﬁnitions. Let’s deﬁne
an elementary triangle as the smallest ﬁgure drawn by a
triplet of adjacent space-vectors. In other words, an elementary
triangle is a triplet of space-vectors that can be generated
successively to modulate a space-vector reference. Its size
(e) a part of the modulation domain determines the resolution of the inverter. Most of the elemen-
Fig. 5. Space vectors and domains generated by the proposed inverter with tary triangles may be generated without commutation of the
a ratio of 3 between input voltages highest-voltage cells. On the contrary, the generation of some
other elementary triangles requires the commutation of the
highest-voltage cells. The ﬁrst category forms the area that we
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have deﬁned as the modulation domain. It corresponds to the B. 3-phase conﬁgurations with higher resolution
area ﬁlled in light grey in Fig. 5(d), where the switching losses
1) Proposed inverter staircase ratings: Let’s continue the
are low. The second category forms an area that is reachable
investigation of the proposed structure with one 3-level H-
by the inverter, with the same accuracy when performing a
bridge per phase. When the ratio between the input voltages
modulation process, but this area cannot be modulated with
is equal to 4, the uniformity condition (1) is not fulﬁlled, 6
the same base vectors and the switching losses are high. In
non-uniform levels are generated. The output voltage range is
Fig. 5(d) this surface is ﬁlled in white in periphery.
one step larger with the same number of levels, hence the step
A conﬁguration is suitable for modulation if there is no
between the levels -1 and 1 is doubled, as represented in the
hole in its modulation domain. When there are holes, it is
state-space in Fig. 4(c). Although the levels are not uniformly
not suitable, because a reference crossing these holes will
distributed, the space vectors are uniformly spread in the α-β
cause many simultaneous commutations. Any reference can
plane, as it can be veriﬁed in Fig. 4(c). 121 space vectors are
be modulated without repeated simultaneous commutations in
generated, i.e. 30 more than with a ratio of 3. With the same
the modulation domain area.
resulting step, a larger magnitude can be generated. Looking
Applying strictly this concept, the reference shouldn’t leave
at the modulation domain, we can see that there are areas
the modulation domain. If this rule is respected, a part of
where the inverter can’t be modulated without simultaneous
the area reachable by the inverter is lost, in a way the new
commutations: there are holes. Thus, this conﬁguration is ill-
conﬁgurations are not so advantageous. In our example, the
suited for modulation. Nevertheless, this conﬁguration seems
reference shouldn’t cross the 6 triangles in periphery which
valid for a staircase output voltage, since there is a large
don’t belong to the modulation domain. Practically, if only
contiguous area covered by the elementary triangles.
a fraction of the reference doesn’t belong to the modulation
domain, it has no major inﬂuence on the high-voltage cell 2) Uniformity domain: Let’s deﬁne the uniformity domain
switching frequency and it is acceptable. In such cases, we as the area that is covered by the elementary triangles as
have two alternatives: represented in grey in Fig. 4(c). This domain is the area where a
reference can be followed with a given accuracy: this accuracy
• either the reference is modulated, which increases the is deﬁned by the size of the elementary triangles.
The reference shouldn’t leave the uniformity domain, but at
• or the closest space-vector to the reference is chosen,
the price of a loss of accuracy, the reference may also cross
which affects the output quality instead of the switching
the areas outside the uniformity domain in periphery — paint
in white in Fig. 4(c). In this way larger magnitudes may be
3) Three-phase modulation condition: the general three- generated.
phase modulation condition can be expressed geometrically as 3) Three-phase uniformity condition: the general three-
the absence of holes in the modulation domain. phase uniformity condition geometrically expresses as the
It can be shown that any 3-phase inverter fulﬁlling the uni- absence of holes in the uniformity domain.
formity condition (1) may be modulated without simultaneous For two cells with hexagonal uniformity domains, the uni-
commutations except in several places in periphery. When the formity condition may be expressed as follow:
number of levels of the low-voltage cell group is higher than
5, some additional conﬁgurations are available, and the three- n1 − 1
phase modulation condition for two cells with an hexagonal ∆U1 ≤ ∆U2 ≤ n1 + · ∆U1 ∀n1 odd
space-vectors set is: (4)
n1 − 2
∆U1 ≤ ∆U2 ≤ n1 + · ∆U1 ∀n1 even
n1 − 3
∆U1 ≤ ∆U2 ≤ n1 + · ∆U1 ∀n1 odd
2 −1 −2
The quantities n12 , respectively n12 in (4) express the
n1 − 4 gain of conﬁgurations compared to the single phase uniformity
∆U1 ≤ ∆U2 ≤ n1 + · ∆U1 ∀n1 even condition (1).
The algebraic expression of the uniformity condition for
The quantities 1 + n12 , respectively 1 + n12 in (3) domain of non-hexagonal shapes is much more complex to
express the gain of conﬁgurations compared to the single phase express. In this case, the help of a simulation tool is useful.
modulation condition (2). We have developed such a tool and the presented graphs were
4) Experimental validation: Practically, the fulﬁllment of obtained using it.
the modulation condition means that slow switches with low 4) Experimental validation: In Fig. 11, we observe that
conduction losses may be used for the high-voltage cell. although the leg voltage generates 6 unevenly-spaced levels,
In Fig. 10, we verify that there are only two simultaneous the line to line voltage generates 13 regularly-spaced levels,
commutations per phase during a period. The narrow pulses as if there were 7 evenly-spaced levels on the leg voltage.
that occur when switching several cells simultaneously are Fig. 11(d) shows the measurements of the 121 space vectors
canceled and there is a little ripple on the current waveform. generated by a spiral space vector reference.
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high voltage cell high voltage cell
low voltage cell low voltage cell
(a) cell space vectors (b) space vector combinations (a) cell space vectors (b) space vector combinations
(c) uniformity domain (d) modulation domain
(c) uniformity domain (d) modulation domain
Fig. 6. Space vectors and domains generated by the proposed inverter with
a ratio of 4 between input voltages Fig. 7. Space vectors and domains generated by the proposed inverter with
a ratio of 5 between input voltages
5) Further investigations: Let’s continue the investigation
To apply this algorithm, the maximum reachable magnitude
with a ratio of 5 between the input voltages. The 133 generated
must be known for several set of cells. This value varies,
space vectors, the uniformity domain and the modulation
because it is limited by an hexagon (or a more complex
domain are shown in Fig. 7. In Fig. 7(c), we can see that the
polygon), hence it varies as a function of the reference angle.
uniformity domain has holes, not only in the periphery but also
To simplify the computations, the maximum magnitude may be
in the medium magnitude area. Furthermore, the modulation
taken constant. The associate domain is a circle circumscribed
domain is constituted by several distinct areas as shown in Fig.
in the low voltage cell hexagon.
This method allows to reduce the simultaneous commuta-
C. Inverter control tions, it is optimal for most trajectories, but not for all, because
A common mode voltage trajectory different from zero the circles don’t cover the whole surfaces of the hexagons.
is followed in order to ensure the proper working of the An example of a circular trajectory generated according to
new additional conﬁgurations. As a consequence, the common this method is shown in Fig. 10. This method is also valid for
mode voltage is often ﬁxed and a strategy, as this proposed the conﬁgurations observing the 3-phase uniformity condition,
in  for the unsupplied cell DC-voltage balance, cannot be but, in this case, the radius has to be chosen larger to cover
applied. the whole uniformity domain. Fig. 11 shows the waveforms
The control is vectorial and is derived from the optimal obtained for a staircase output.
scalar method proposed in  and from the recursive method D. Performance evaluation
presented in , . It allows to minimize the simultaneous
commutations whatever the reference trajectory. In Fig. 1(b)(c) and 2(b), some conﬁgurations and their
The actual space-vector state of the highest-voltage cell is properties are summarized :
subtracted from the reference space vector. If the result is • u means single-phase uniformity condition (1) is fulﬁlled,
smaller or equal to the maximum magnitude reachable by the • m both condition (1) and single-phase modulation condi-
other cells, then the high-voltage cell state remains unchanged. tion (2) are fulﬁlled,
There is no commutation of this cell and the remainder is used • vu means the space vectors are evenly spread, i.e. three-
as reference for the other cells. If the remainder is greater than phase uniformity condition (4) is fulﬁlled,
the maximum magnitude reachable by the other cells, then the • vm means that in addition they can be modulated, i.e.
high-voltage cell state must be modiﬁed to reach the reference both condition (4) and three-phase modulation condition
position. In this case, the nearest space vector to the reference (3) are fulﬁlled.
is chosen as the new state for the high-voltage cell. This value One can wonder what is the inﬂuence of the areas in
is subtracted from its reference to get the reference for the periphery which doesn’t belong to the modulation domain or
other cells. This process is recursive, it is repeated for the next to the uniformity domain. For that purpose, Fig. 8 compares
cells in descending order of voltage. several conﬁguration under quantiﬁcation, i.e. selection of the
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closest space-vectors to the reference. The ﬁrst simulation in A. Prototype description
Fig. 8(a) compares three conﬁgurations: In this section, the prototype characteristics are presented.
1) the most asymmetrical conﬁguration for the proposed The switch ratings are 600 V 30 A and 1200 V 15 A for the
topology under the single-phase uniformity condition (1), IGBTs and 100 V 30 A for the MOSFETs. The prototype is
2) the most asymmetrical conﬁguration for the proposed versatile, it consists of a multi-winding transformer and boards
topology under the three-phase uniformity condition (4), (PCB) with 3 H-bridges each. The H-bridges and transformer
3) a conﬁguration with the same space-vectors set as 2), terminals are connected with standard laboratory wires and
but with the holes in periphery completed. connectors to get the tested — or any other desired — topology.
The topology represented in Fig. 2 requires four PCBs. The
The comparison was realized with a circular (sine) reference.
control functions are executed by a DSP board . The
As expected, for most magnitudes, conﬁgurations 2) and 3) are
control algorithms of the multilevel inverter and of the DC-
identical and better than 1). For high magnitudes, conﬁguration
DC converter are implemented by a C program. They are
2) meets and is ﬁnally worse than conﬁguration 1).
running in the same DSP, while the PWM multilevel modulator
The second simulation in Fig. 8(b) compares the same is implemented in an on-board FPGA.
conﬁgurations as previously, but with a different topology. The
3-phase H-bridge inverter has been replaced by a three-phase B. Energetic efﬁciency measurements
three-level N.P.C inverter as studied in . In this latter case The energetic efﬁciency was measured and compared to
conﬁguration 2) is always better than conﬁguration 1). its simulated values. The results are shown in Fig. 9 for
a set of sine references for a constant output current on a
THD1 resistive-inductive load. The measured structure is the proposed
THD2 one with a three-phase H-bridge inverter with 600 V IGBT
−10 devices and with one 3-level H-bridge per phase with 100 V
MOSFET devices. For this test, the cell input voltages were
120V respectively 40V, the output load current was 3A for
a magnitude going from 15 % to 115 %. The experimental
results match the simulated one except for low magnitudes.
−20 This error is probably due to the bad knowledge of iron losses
and to the DC-DC modelisation that is not enough accurate.
For low magnitudes, these latter losses are predominant. The
0 0.2 0.4 0.6 0.8 1 energetic efﬁciency is quite low in this case, because the choice
of the MOSFET cell for this measurement limits the inverter
operating voltage. When the IGBT blocking capabilities are
1 used at their nominal values, the efﬁciency is better.
0.6 ideal case
0 0.2 0.4 0.6 0.8 1
(b) 0 0.2 0.4 0.6 0.8 1
Fig. 8. Performance evaluation for different conﬁgurations (a) proposed
structure with one three-level H bridge per phase (b) 3-phase 3-level N.P.C. Fig. 9. Theoretical and experimental energetic efﬁciency: ∆U1 = 40 V ,
inverter with one three-level H bridge in series per phase (curves : × max. vu ∆U2 = 120 V , iload = 3 A, PWM frequency fp = 20 kHz, DC-DC
; ◦ max u ; + u equivalent to max. vu). frequency fdc−dc = 20 kHz, circular reference, magnitude going from 15 %
to 115 %.
V. E XPERIMENTAL VALIDATION VI. C ONCLUSIONS
The asymmetrical multilevel inverter is an advantageous
A prototype was built to validate the proposed concepts. The structure to obtain a high resolution. We have proposed a
results of Fig. 10 and 11 have already been presented in IV-A.4 way to reduce the number of insulated supplies and to im-
respectively in IV-B.4. prove the energetic efﬁciency. So far, for PWM applications,
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200 200 120 1.5
150 150 100
100 100 80
50 50 60
0 0 40 0
−50 −50 20
−100 −100 0
−150 −150 −20
−200 −200 −40 −1.5
0 20 40 60 80 100 0 20 40 60 80 100
(a) leg voltage (b) high voltage (a) leg voltage (b) line current
200 10 pab0f
150 line 1
0 0 50
−200 −10 −100
(c) low voltage (d) line current −150
0 20 40 60 80 100 -80
-100 -80 -60 -40 -20 0 20 40 60 80 100
100 (c) line to line voltage (d) measured space vectors
Fig. 11. M = 3.25 · ∆U = 108% With a ratio of 4 between input voltages,
the resolution and consequently the current are improved.
−200  A. Rufer, M. Veenstra, and K. Gopakumar. Asymmetric multilevel
converter for high resolution voltage phasor generation. EPE’99.
(e) line to line voltage  P.K. Steimer and M.D. Manjrekar. Practical medium voltage converter
Fig. 10. Investigated topology with voltage ratio of 3. M = 2.0 · ∆U = topologies for high power applications. IAS’2001 Conference Proceed-
80%: with the appropriate vector control strategy, the repeated simultaneous ings, 3:1723–1730, September 2001.
commutations do not occur  M. Veenstra and A. Rufer. Control of a hybrid asymmetric multi-level
inverter for competitive medium-voltage industrial drives. IAS’2003,
1:190 – 197, October 2003.
 S. Mariethoz and A.C. Rufer. Design and control of asymmetrical multi-
the conﬁgurations with the highest known resolution were level inverters. IECON’02, November 2002.
 M.R. Baiju and K. Gopakumar et al. A high resolution multilevel voltage
rejected. We have shown that this problem can be overcome space phasor generation for an open-end winding induction motor drive.
for three-phase applications and that these previously rejected EPE Journal, 13(4), 2003.
conﬁgurations are usable. In addition, some new conﬁgurations  B.S. Suh, Y.H. Lee, D.S. Hyun, and T.A. Lipo. A new multilevel inverter
topology with a hybrid approach. EPE’99.
with even higher resolution have been proposed, either for a  M. Veenstra. Investigation and Control of a Hybrid Asymmetric Multi-
step-stair voltage or for a modulated one. The new available Level Inverter for Medium-Voltage Applications. PhD thesis, École
conﬁgurations extend the design ﬂexibility and the possibilities Polytechnique Fédérale de Lausanne, Lausanne (CH), 2003.
 C. Rech, H.A. Grundling, H.L. Hey, H. Pinheiro, and J.R. Pinheiro.
to optimize the combined device matching. They are not only A generalized design methodology for hybrid multilevel inverters.
valid for the proposed structure, but also for other asymmetrical IECON’02, November 2002.
topologies. The effectiveness of the proposed structure and  N.P. Schibli, A. Schaller, and A.C. Rufer. Online vector modulation and
control for three-phase multilevel inverter. NORPIE98, 1998.
designs is experimentally veriﬁed.  CHS Engineering. DAVID Development system, 2002. Available:
 A. Nabae and H. Akagi. A new neutral-point-clamped PWM inverter.
IEEE Transactions on Industry Applications, 17(5):518–523, September
 T. Meynard and H. Foch. Multi-level choppers for high voltage
applications. EPE Journal, 2(1):45–50, 1992.
 M. Marchesoni, M. Mazzucchelli, and S. Tenconi. A non conventional
power converter for plasma stabilization. PESC’88, 1:122–129.
 O.M. Mueller and J.N. Park. Quasi-linear IGBT inverter topologies.
APEC’94 Conference Proceedings, 1:253–259, February 1994.
 M.D. Manjrekar, P.K. Steimer, and T.A. Lipo. Hybrid multilevel power
conversion system : A competitive solution for high power applications.
IEEE Transations On Industry Applications, 36(3):834–841, May/June
 K.A. Corzine, S.D. Sudhoff, and C.A. Whitcomb. Performance charac-
teristics of a cascaded two-level converter. IEEE Transactions on Energy
Conversion, 14(3), September 1999.
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