# l5-ind

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Chapter 5 Interconnect RLC Model

   Efficient capacitance model

Efficient inductance model
RC and RLC circuit model generation

   Numeric based interconnect modeling
Is RC Model still Sufficient?

   Interconnect impedance is more than resistance
Z   R +jL
   1/tr

   On-chip inductance should be considered
 When  L becomes comparable to R as we move
towards Ghz+ designs
Candidates for On-Chip Inductance
   Wide clock trees
 Skews are different under RLC and RC models
 Neighboring signals are disturbed due to large clock di/dt
noise

   Fast edge rate (~100ps) buses
 RC   model under-estimates crosstalk

   P/G grids (and C4 bumps)
 di/dt   noise might overweight IR drop
Resistance vs Inductance
Length = 2000, Width = 0.8
Thickness = 2.0, Space = 0.8

200                                                                3.20E-09
180
3.10E-09
160
3.00E-09
140

Inductance(H)
Reactance

120                                                                2.90E-09                                             Self
R
100                                                                                                                     mutual
wL                   2.80E-09
80
60                                                                 2.70E-09

40                                                                 2.60E-09
20
2.50E-09
0                                                                     1.00E+08     1.00E+10   1.00E+12     1.00E+14
1.00E+08   1.00E+09    1.00E+10    1.00E+11
frequency (100M-100G)                                                   frequency (100M-100T)Hz

R and L for a single wire                                       Ls and Lx for two parallel wires
Impact of Inductance

5u   10u    5u
Gnd   Clk   Gnd

RC model                 RLC model
Inductance Extraction from Geometries
   Numerical method based on Maxwell’s equations
   Accurate, but way too slow for iterative physical design
and verification

   Efficient yet accurate models
   Coplanar bus structure [He-Chang-Shen-et al, CICC’99]
   Strip-lines and micro-strip bus lines [Chang-Shen-He-et al,
DATE’2K]
   Used in HP for state-of-the-art CPU design
Definition of Loop Inductance
Ii                            Ij

Vi                                                    Vj

   The loop inductance is

   1      1                           1
Lij            
4 ai a j I i I j    
loopi ai
 a rij dIi dI j dai da j
loop j j
Loop Inductance for N Traces
TwL         Tw        Tw        Tw         TwR      1.73 1.15 0.53
1.15 1.94 1.24
TsL        Ts        Ts        TsR            0.53 1.24 1.92
tL          t1        t2    t3             tR

   Assume edge traces are AC-grounded
 leads      to 3x3 loop inductance matrix
   Inductance has a long range effect
 non-negligible                 coupling between t1 and t3, even with t2
between them
It is not sufficient to consider only a single net,
as did by most interconnect modeling and
optimization works
Table in Brute-Force Way is Expensive
TwL         Tw        Tw        Tw         TwR   1.73 1.15 0.53
1.15 1.94 1.24
TsL        Ts        Ts        TsR         0.53 1.24 1.92
tL          t1        t2    t3             tR

   Self inductance has nine dimensions:
   (n, length, location,TwL,TsL,Tw,Ts,TwR,TsR)
   Mutual inductance has ten dimensions:
   (n, length, location1, location2,TwL,TsL,Tw,Ts,TwR,TsR)
   Length is needed because inductance is not linearly
scalable
Definition of Partial Inductance
ci     cj

Vi       li                     lj            Vj

bi     bj

   Partial inductance is the portion of loop inductance
for a segment when its current returns via the
infinity
 called   partial element equivalent circuit (PEEC) model
   If current is uniform (no skin effect), the partial
inductance is
cj

ci
1           dli dl j
Lij                      dai da j
4 ai a j b a b a rij
i    i    j   j
Partial Inductance for N Traces
TwL          Tw        Tw        Tw         TwR   6.17   5.43   5.12   4.89   4.66
5.43   6.79   6.10   5.48   5.04
TsL        Ts        Ts        TsR         5.12   6.10   6.79   6.10   5.33
tL           t1        t2    t3             tR    4.89   5.48   6.10   6.79   5.77
4.66   5.04   5.33   5.77   6.50

   Treat edge traces same as inner traces
     lead to 5x5 partial inductance table
   Partial inductance model is more accurate
compared to loop inductance model
     Without pre-setting current return loop
Foundation I
The self inductance under the PEEC model
for a trace depends only on the trace itself
(w/ skin effect for a given frequency).

6.17   5.43   5.12   4.89   4.66
TwL         Tw        Tw        Tw         TwR   5.43   6.79   6.10   5.48   5.04
5.12   6.10   6.79   6.10   5.33
TsL        Ts        Ts        TsR         4.89   5.48   6.10   6.79   5.77
tL          t1        t2    t3             tR    4.66   5.04   5.33   5.77   6.50

6.50
Foundation II
The mutual inductance under the PEEC model for
two traces depends only on the traces themselves
(w/ skin effect for given frequency).

6.17   5.43   5.12   4.89   4.66
TwL         Tw        Tw        Tw         TwR   5.43   6.79   6.10   5.48   5.04
5.12   6.10   6.79   6.10   5.33
TsL        Ts        Ts        TsR         4.89   5.48   6.10   6.79   5.77
tL          t1        t2    t3             tR    4.66   5.04   5.33   5.77   6.50

6.17                        4.66
4.66                        6.50
Foundation III
The self loop inductance for a trace on top
of a ground plane depends only on the trace
itself (its length, width, and thickness)

TwL         Tw        Tw        Tw         TwR   4.8 2.5    1.3   0.7   0.14
2.5 5.5    2.9   1.5   0.7
TsL        Ts        Ts        TsR         1.3 2.9    5.7   2.9   1.3
tL          t1        t2    t3             tR    0.7 1.5    2.9   2.5   2.5
0.14 0.7   1.3   2.5   4.8

4.8
tR
Foundation IV
The mutual loop inductance for two traces on
top of a ground plane depends only on the two
traces themselves
(their lengths, widths, and thickness)

TwL         Tw        Tw        Tw         TwR   4.8 2.5    1.3   0.7   0.14
2.5 5.5    2.9   1.5   0.7
TsL        Ts        Ts        TsR         1.3 2.9    5.7   2.9   1.3
tL          t1        t2    t3             tR    0.7 1.5    2.9   2.5   2.5
0.14 0.7   1.3   2.5   4.8

4.8                    0.14
tL                                         tR   0.14                   4.8
Validation and Implication of Foundations
 Foundations I and II can be validated
theoretically
 Foundations III and IV were verified
experimentally
 Problem size of inductance extraction can be
greatly reduced w/o loss of accuracy
 Solve 1-trace problem for self inductance
 Reduce 9-D table to 2-D table

 Solve 2-trace problem for mutual inductance
 Reduce 10-D table to 3-D table
Analytical Solutions to Inductance
Not suitable for on-chip interconnects

    Without considering skin effect and
internal inductance
2l
 Self   inductance     L(nH )  2l  [ln(       )  0.5  k ]
   k=f(w,t)                               wt
0 < k < 0.0025
l       2l      s
 Mutual inductance L(nH )      [ln( )  1  ]
2       s       l

   Inductance is not sensitive to width,
thickness and spacing
 Noneed to consider process variations for
inductance
Extension to Random Nets
[Xu-HE, GLSVLSI’01]
   Nets with arbitrary locations, lengths, thickness, and etc.
   available as a web-based tool http://eda.ece.wisc.edu/WebHenry

   Mutual inductance Lab =
a
b

Mutual inductance

+           -                -
Lm1            Lm2            Lm3              Lm4
Accuracy

   Table versus FastHenry
   400 random displaced parallel wires cases
Error Distribution

 5% most cases
 Bigger error only found in smaller inductance values
Full RLC Circuit Model
Ls(wire12)

\$\$ Self inductance \$\$
L11 N11 N12 val
N13                L12 N13 N14 val
N11           N12                 N14
L21 N21 N22 val
L22 N23 N24 val
\$\$ mutual inductance \$\$
N23                K1 L11 L21 val
N21           N22                 N24
K2 L12 L22 val
K3 L11 L12 val
K4 L21 L22 val
K5 L11 L22 val
K6 L21 L12 val

   For n wire segments per net
   RC elements: n                Lm(wire21, wire12) / sqrt(L21 * L12)
   self inductance: n
   mutual inductance: n*(n-1)
Normalized RLC Circuit Model
Ls(net1)

\$\$ Self inductance \$\$
L11 N11 N12 val
N13              L12 N13 N14 val
N11          N12               N14
L21 N21 N22 val
L22 N23 N24 val
\$\$ mutual inductance \$\$
N23              K1 L11 L21 val
N21           N22              N24
K2 L12 L22 val

   For n segments per wire           Lm(net1, net2) / sqrt(net1 * net2)
   RC elements: n
   Self inductance: n
   Mutual inductance: n
Full Versus Normalized

   Two waveforms are almost identical
   Running time:
   Full         99.0 seconds
   Normalized   9.1 seconds
Application of RLC model:
Shielding Insertion

   To decide a uniform shielding structure for a given
wide bus
   Ns: number of signal traces between two shielding traces
   Ws: width of shielding traces

Ws                          Ws                          Ws
...                         ...
1   2   3         Ns        1   2   3         Ns
Trade-off between Area and Noise
   Total 18 signal traces
 2000um  long, 0.8um wide
 separated by 0.8um

   Drivers --130x; Receivers -- 40x
   Power supply: 1.3V

Ns     Ws    Noise(v)   Routing Area (um)   Wire Area (um)
18     --    0.71       61.1(0.0%)          46.4(0.0%)
6      0.8   0.38       64.8                48.0
6      1.6   0.27       66.4                49.6
6      2.4   0.22       68.0                51.2
3      0.8   0.17       69.6(13%)           50.4(8.8%)
Conclusions
   Inductance is a long-range effect
   Inductance can be extracted efficiently use
PEEC model
   Normalized RLC circuit model with a much reduced
complexity can be used for buses
   Full RLC circuit model should be used for random nets
   Model reduction or sparse inductance model may reduce circuit
complexity
   RLC circuit model may be simulated for interconnect
optimization

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