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VIEWS: 25 PAGES: 4

									Symbol            Pin   Type                      Description                                 Assignement

                               Port 0 is a 32-bit bidirectional I/O port with
                               individual direction controls for each bit. The
P0[0] to P0[31]         I/O    operation of port 0 pins depends upon the pin
                               function selected via the Pin Connect Block. Pins
                               26 and 31 of port 0 are not available.
P0[0]/TXD0/              O     TXD0 — Transmitter output for UART0.                 TXD0 — Transmitter output for
                  19
PWM1                     O     PWM1 — Pulse Width Modulator output 1.               UART0.
                         I     RXD0 — Receiver input for UART0.
P0[1]/RXD0/                                                                         RXD0 — Receiver input for
                  21     O     PWM3 — Pulse Width Modulator output 3.
PWM3/EINT0                                                                          UART0.
                         I     EINT0 — External interrupt 0 input
                        I/O    SCL — I2C-bus clock input/output. Open-drain         SCL — I2C-bus clock input/output.
P0[2]/SCL/
                  22           output (for I2C-bus compliance).                     Open-drain output (for I2C-bus
CAP0[0]
                         I     CAP0[0] — Capture input for Timer 0, channel 0.      compliance).
                        I/O    SDA — I2C-bus data input/output. Open-drain
                                                                                    SDA — I2C-bus data input/output.
P0[3]/SDA/                     output (for I2C-bus compliance).
                  26                                                                Open-drain output (for I2C-bus
MAT0[0]/EINT1            O     MAT0[0] — Match output for Timer 0, channel 0.
                                                                                    compliance)
                         I     EINT1 — External interrupt 1 input.
                        I/O    SCK0 — Serial clock for SPI0. SPI clock output
P0[4]/SCK0/
                  27           from master or input to slave.                       LED1 - Output driver led1
CAP0[1]
                         I     I CAP0[1] — Capture input for Timer 0, channel 1.

                        I/O    MISO0 — Master In Slave OUT for SPI0. Data
P0[5]/MISO0/
                  29           input to SPI master or data output from SPI slave.   LED3 - Output driver led3
MAT0[1]
                         O     MAT0[1] — Match output for Timer 0, channel 1.

                        I/O    MOSI0 — Master Out Slave In for SPI0. Data
P0[6]/MOSI0/
                  30           output from SPI master or data input to SPI slave.   LED4 - Output driver led4
CAP0[2]
                         I     CAP0[2] — Capture input for Timer 0, channel 2.

                         I     SSEL0 — Slave Select for SPI0. Selects the SPI
P0[7]/SSEL0/                   interface as a slave.                                A_SEG - Output driver seg. A
                  31
PWM2/EINT2               O     PWM2 — Pulse Width Modulator output 2.               display
                         I     EINT2 — External interrupt 2 input.

P0[8]/TXD1/              O     TXD1 — Transmitter output for UART1.
                  33                                                                GA0 - Input geographic address 0
PWM4                     O     PWM4 — Pulse Width Modulator output 4.

                         I     RXD1 — Receiver input for UART1.
P0[9]/RXD1/
                  34     O     PWM6 — Pulse Width Modulator output 6.               GA1 - Input geographic address 1
PWM6/EINT3
                         I     EINT3 — External interrupt 3 input.

P0[10]/RTS1/             O     RTS1 — Request to Send output for UART1.
                  35                                                                GA2 - Input geographic address 2
CAP1[0]                  I     CAP1[0] — Capture input for Timer 1, channel 0.

P0[11]/CTS1/             I     CTS1 — Clear to Send input for UART1.
                  37                                                                GA3 - Input geographic address 3
CAP1[1]                  I     CAP1[1] — Capture input for Timer 1, channel 1.


P0[12]/DSR1/             I     DSR1 — Data Set Ready input for UART1.
                  38                                                                GA4 - Input geographic address 4
MAT1[0]                  O     MAT1[0] — Match output for Timer 1, channel 0.
P0[13]/DTR1/           O     DTR1 — Data Terminal Ready output for UART1.
                  39                                                                GA5 - Input geographic address 5
MAT1[1]                O     MAT1[1] — Match output for Timer 1, channel 1.

                        I    DCD1 — Data Carrier Detect input for UART1.
                        I    EINT1 — External interrupt 1 input.
P0[14]/DCD1/
                  41         Note: LOW on this pin while RESET is LOW forces        BOOTLDR – Input (open/gnd)
EINT1
                             on-chip bootloader to take control of the part after
                             reset.

P0[15]/RI1/             I    RI1 — Ring Indicator input for UART1.
                  45                                                                GA7 - Input geographic address 7
EINT2                   I    EINT2 — External interrupt 2 input.

P0[16]/EINT0/          I     EINT0 — External interrupt 0 input.
                                                                                    F_SEG - Output driver seg. F
MAT0[2]/          46   O     MAT0[2] — Match output for Timer 0, channel 2.
                                                                                    display
CAP0[2]                I     CAP0[2] — Capture input for Timer 0, channel 2.

                         I   CAP1[2] — Capture input for Timer 1, channel 2.
P0[17]/
                       I/O   SCK1 — Serial Clock for SPI1/SSP [1]. SPI clock        G_SEG - Output driver seg. G
CAP1[2]/          47
                             output from master or input to slave.                  display
SCK1/MAT1[2]
                       O     MAT1[2] — Match output for Timer 1, channel 2.
                         I   CAP1[3] — Capture input for Timer 1, channel 3.
P0[18]/
                       I/O   MISO1 — Master In Slave Out for SPI1/SSP [1].
CAP1[3]/
                  53         Data input to SPI master or data output from SPI       GA6 - Input geographic address 6
MISO1/
                             slave.
MAT1[3]
                        O    MAT1[3] — Match output for Timer 1, channel 3.
                        O    MAT1[2] — Match output for Timer 1, channel 2.
P0[19]/
                       I/O   MOSI1 — Master Out Slave In for SPI1/SSP [1].
MAT1[2]/
                  54         Data output from SPI master or data input to SPI       PULS2 - Input dev/mom open/gnd
MOSI1/
                             slave.
CAP1[2]
                        I    CAP1[2] — Capture input for Timer 1, channel 2.
                       O     MAT1[3] — Match output for Timer 1, channel 3.
P0[20]/
                       I     SSEL1 — Slave Select for SPI1/SSP [1]. Selects
MAT1[3]/          55                                                                PULS1 - Input dev/mom open/gnd
                             the SPI interface as a slave.
SSEL1/EINT3
                        I    EINT3 — External interrupt 3 input.

P0[21]/PWM5/           O     PWM5 — Pulse Width Modulator output 5.
                  1                                                                 MUXSEL0 - Output to multiplexer
CAP1[3]                I     CAP1[3] — Capture input for Timer 1, channel 3.

P0[22]/CAP0[0]/        I     CAP0[0] — Capture input for Timer 0, channel 0.
                  2                                                                 MUXSEL1 - Output to multiplexer
MAT0[0]                O     MAT0[0] — Match output for Timer 0, channel 0.

                             RD2 — CAN2 receiver input (not available on
  P0[23]/RD2      3     I                                                           MUXEN0 - Output to multiplexer
                             LPC2109).


                             TD2 — CAN2 transmitter output (not available on
  P0[24]/TD2      5    O                                                            MUXEN2 - Output to multiplexer
                             LPC2109).


  P0[25]/RD1      9     I    RD1 — CAN1 receiver input.                             RD1 — CAN1 receiver input


                        I    AIN0 — A/D converter, input 0. This analog input is
P0[27]/AIN0/                                                                        AIN0 — A/D converter, input 0.
                             always connected to its pin.
CAP0[1]/          11                                                                Voltage level monitor. (5V, 3.3V,
                       I     CAP0[1] — Capture input for Timer 0, channel 1.
MAT0[1]                                                                             1.8V)
                       O     MAT0[1] — Match output for Timer 0, channel 1.
                        I    AIN1 — A/D converter, input 1. This analog input is
P0[28]/AIN1/                                                                       AIN1 — A/D converter, input 1.
                             always connected to its pin.
CAP0[2]/          13                                                               Voltage level monitor. (+/-9V,
                       I     CAP0[2] — Capture input for Timer 0, channel 2.
MAT0[2]                                                                            +/-VIN)
                       O     MAT0[2] — Match output for Timer 0, channel 2.

                        I    AIN2 — A/D converter, input 2. This analog input is
P0[29]/AIN2/
                             always connected to its pin.                          AIN2 — A/D converter, input 2.
CAP0[3]/          14
                       I     CAP0[3] — Capture input for Timer 0, Channel 3.       Not filtered level monitor.
MAT0[3]
                       O     MAT0[3] — Match output for Timer 0, channel 3.

                        I    AIN3 — A/D converter, input 3. This analog input is
P0[30]/AIN3/                 always connected to its pin.                          AIN3 — A/D converter, input 3.
                  15
EINT3/CAP0[0]           I    EINT3 — External interrupt 3 input.                   Filtered level monitor.
                        I    CAP0[0] — Capture input for Timer 0, channel 0.
                             Port 1 is a 32-bit bidirectional I/O port with
                             individual direction controls for each bit.
                             The operation of port 1 pins depends upon the pin
P1[0] to P1[31]        I/O
                             function selected via the Pin
                             Connect Block. Pins 0 through 15 of port 1 are not
                             available.
P1[16]/                      TRACEPKT0 — Trace Packet, bit 0.
                  16   O                                                           Open
TRACEPKT0                    Standard I/O port with internal pull-up.

P1[17]/                      TRACEPKT1 — Trace Packet, bit 1.
                  12   O                                                           Open
TRACEPKT1                    Standard I/O port with internal pull-up.
                                                                                   CANSEL — Input CAN bus
P1[18]/                      TRACEPKT2 — Trace Packet, bit 2.
                  8    O                                                           selection. Forced LOW when front-
TRACEPKT2                    Standard I/O port with internal pull-up.
                                                                                   panel connector plugged-in.
P1[19]/                      TRACEPKT3 — Trace Packet, bit 3.
                  4    O                                                           MUXEN1 - Output to multiplexer
TRACEPKT3                    Standard I/O port with internal pull-up.
                             TRACESYNC — Trace Synchronization.
                             Standard I/O port with internal pull-up.
P1[20]/                                                                            DP_SEG - Output driver dot point
                  48   O     Note: LOW on this pin while RESET is LOW,
TRACESYNC                                                                          display
                             enables pins P1[25:16] to operate as
                             Trace port after reset.
P1[21]/                      Pipeline Status, bit 0.                               E_SEG - Output driver seg. E
                  44   O
PIPESTAT0                    Standard I/O port with internal pull-up.              display
P1[22]/                      Pipeline Status, bit 1.                               D_SEG - Output driver seg. D
                  40   O
PIPESTAT1                    Standard I/O port with internal pull-up.              display
P1[23]/                      Pipeline Status, bit 2.                               C_SEG - Output driver seg. C
                  36   O
PIPESTAT2                    Standard I/O port with internal pull-up.              display
P1[24]/                      Trace Clock.                                          B_SEG - Output driver seg. B
                  32   O
TRACECLK                     Standard I/O port with internal pull-up.              display
P1[25]/                      External Trigger Input.
                  28    I                                                          LED2 - Output driver led2
EXTIN0                       Standard I/O with internal pull-up.
                             RTCK - Returned Test Clock output. Extra signal
                             added to the JTAG port. Assists debugger
                             synchronization when processor frequency varies.
                                                                                   RTCK - Returned Test Clock
P1[26]/RTCK       24   I/O   Bidirectional pin with internal pull-up.
                                                                                   output.
                             Note: LOW on this pin while RESET is LOW,
                             enables pins P1[31:26] to operate as
                             Debug port after reset.

P1[27]/TDO        64   O     TDO -Test Data Out for JTAG interface.                TDO -Test Data out for JTAG.
P1[28]/TDI    60    I   TDI - Test Data In for JTAG interface.                 TDI - Test Data In for JTAG.

                        TCK - Test Clock for JTAG interface. This clock
P1[29]/TCK    56    I   must be slower than 16 of the CPU clock               TCK - Test Clock for JTAG.
                        (CCLK) for the JTAG interface to operate.

P1[30]/TMS    52    I   TMS - Test Mode Select for JTAG interface.             TMS - Test Mode Select for JTAG.


P1[31]/TRST   20    I   TRST -Test Reset for JTAG interface.                   TRST -Test Reset for JTAG.


TD1           10    O   TD1 - CAN1 transmitter output.                         TD1 - CAN1 transmitter output.

                        External reset input; a LOW on this pin resets the
                        device, causing I/O ports and
RESET         57    I   peripherals to take on their default states, and       RESETB - Reset
                        processor execution to begin at
                        address 0. TTL with hysteresis, 5 V tolerant.

                        Input to the oscillator circuit and internal clock
XTAL1         62    I                                                          XTAL1
                        generator circuits


XTAL2         61    O   Output from the oscillator amplifier.                  XTAL2

              6,
              18,
VSS           25,   I   Ground: 0 V reference                                  DGND
              42,
              50

                        Analog ground; 0 V reference. This should
VSSA          59    I   nominally be the same voltage as VSS,                  DGND
                        but should be isolated to minimize noise and error.

                        PLL analog ground; 0 V reference. This should
                        nominally be the same voltage as
VSSA(PLL)     58    I                                                          DGND
                        VSS, but should be isolated to minimize noise and
                        error.

              17,       1.8 V core power supply; this is the power supply
VDD(1V8)            I                                                          V1V8+
              49        voltage for internal circuitry.

                        Analog 1.8 V core power supply; this is the power
                        supply voltage for internalcircuitry. This should be
VDDA(1V8)     63    I                                                          V1V8A
                        nominally the same voltage as V DD(1V8) but should
                        be isolated to minimize noise and error.

              23,
                        3.3 V pad power supply; this is the power supply
VDD(3V3)      43,   I                                                          V3V3+
                        voltage for the I/O ports.
              51

                        Analog 3.3 V pad power supply; this should be
                        nominally the same voltage as
VDDA(3V3)      7    I                                                          VPLL
                        VDD(3V3) but should be isolated to minimize noise
                        and error.

								
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