22| wir elessdesignmag.com V i r t u a l P r o t o t y P e S i m u l at i o n
D e s i g n TA l k
Early 3G Software Development
and Debugging on a Virtual System
Virtual System Prototypes (VSPs) offer a means to develop and debug
embedded software before the silicon is available.
|By Jeff roane, VaSt Systems technology Corp. ed to develop software are typically not modeled or abstracted,
e.g., the RF front-end could be neglected and instead IQ data
s the semiconductor industry continues to consolidate in the baseband domain is used.
off-the-shelf hardware components to build wire- The key is that such a VSP is fast and accurate to ensure
less consumer devices, such as 3G phones, these that full software loads, e.g., complete protocol stacks and
devices are increasingly differentiated by software content. operating systems can be executed in a decent time. The
The iPhone® is a great example of that trend. In a time where accuracy is mandatory to verify whether the software fulfills
the overall market is in decline, the iPhone uses an off-the- real-time constraints, e.g., processing frames within the rates
shelf ARM-based application processor, differentiated by a defined in a wireless standard.
software-based intuitive human machine interface and new
application features. Achieving the Required Speed
As the focus definitely shifts from hardware to embedded Binary translation techniques are used to achieve the nec-
software, new methodologies must be applied to ensure the essary speed of such a virtual simulation and the concept is
requested functionality implemented by increasing numbers to emulate the instructions of the embedded processor on the
As the focus definitely shifts from hardware to embedded software, new methodologies
must be applied to ensure the requested functionality implemented by increasing numbers
of lines of code is completed when the product is shipped.
of lines of code is completed when the product is shipped. host machine, typically an x86 architecture. The goal is to use
Virtual System Prototypes (VSPs) offer a means to develop as few instructions as possible on the host machine in order
and debug embedded software before the silicon is available. to emulate the embedded CPU to achieve high simulation
speeds. As the simulation speed depends on many factors,
So What is a VSP? such as the performance of the host machine, complexity of
In short, this is a C/C++/SystemC based simulation model the system, detail of modeling etc., the simulation speed may
of the wireless device that models all the components such as vary a lot − from slower than real-time up to faster than real-
processors, graphic accelerators, peripherals, buses, memo- time. Typically, 1 MIPS is accepted by the software developer
ries etc. and also the testbench to provide stimuli to the wire- community as a minimum speed, and software running mainly
less system. Parts of the system that are not necessarily need- in cache can easily break the 50 MIPS barrier using binary
Application RF Layer 2 Modem
Baseband Protocol Stack
External Processor Tester
Figure 1. Abstract view of a mobile terminal. Figure 2. VSP setup for 3G modem protocol stack development.
24| wirelessdesignmag.com V i r t u a l P r o t o t y P e S i m u l at i o n
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translation techniques. Meeting Real-time Constraints encountered during a function call. It is obvious
Now as the complete wireless system with all In debug mode the 3rd party debuggers such as that these debugging features are used to optimize
its components and stimuli is in place and runs Lauterbach’s Trace32, GreenHill’s Multi5, ARM’s the embedded software with regards to runtime
almost as fast as the real hardware, the software RealView etc. are launched and attached to the to meet real-time constraints. Cycle-accuracy and
can be loaded, executed and, even more important, simulator using a debugging interface. These are modeling of all using case dependent details is
debugged using the same 3rd party tools that also in the scope of standardization bodies, and key for VSPs so that they can be used for pre-sili-
would be attached to the silicon. the Multi-Core Debug (MCD) interface is one con software development.
Of course, the same compiler and debugger tool which is being standardized under the umbrella of An example is when the layered protocol stack
chain as for the traditional flow is used to develop SPRINT. needs to process 3G frames in time. Imagine the
the embedded software and the virtual system pro- The look and feel of this setup is the same as underlying virtual processor model (VPM) does
totype loads exactly like this target (binary) image. if the debugger is attached to the real hardware not implement cache behavior, but those that are
This means that once the real silicon is taped and, of course, all advanced features are supported. contributing most to an increase of software execu-
out, the software image runs immediately without These include instruction tracing, stepping back in tion times as a miss would imply a cache line fill
further porting efforts, which is also due to the time, function profiling, operating system aware usually done by a burst transfer over the instruction
fact that the simulation is cycle-accurate and thus debugging, monitoring events correlated to func- bus. It takes significant time to request the bus,
behaves as the silicon. tion calls, e.g., number of cache hits and misses getting the bus granted after the arbitration took
place and finally fetching bytes over the bus. These
additional cycles dominate the software execu-
. tion time and may violate the real-time constraints
when the software is not yet mainly executed out
Debug in end Product Packages now Possible
D e s i g n TA l k
of cache. It is obvious that a fully arbitrating cycle-
accurate bus is a key element to the overall timing
Stephen lau, Product manager for emulation technology, as well. Imagine the bus is used and locked by
texas instruments When and how you debug an embedded System another master or a second processor in a multi-
core system and the pure functional model does not
on Chip (SoC) wireless device is changing. This is driven by an expansion of
handle arbitration at all.
when debugging can be done. Pure functional VSPs and especially processor
When and how you debug an embedded System on Chip (SoC) wireless models overcome the lack of modeling details
device is changing. This is driven by an expansion of when debugging can be by switching back to a more accurate but slower
model, for example, to get the important timing
done. Previously, debugging was only done in a product development environ-
information caused by a cache miss. Sometimes
ment where the SoC is exposed on a target PCB. With strong time to market pressure decreasing these simulations are called Hybrid Simulation, as
product development schedules, there is an increased need to debug SoC while in the final product. multiple models of a single processor are involved
Debugging SoC while they are in the final product package also allows for debug and optimization and also have to be maintained.
of existing deployed products.
Optimizing the Software Architecture
The proposed Mobile Industry Processor Interface (MIPI), Narrow Interface for Debug and Test With an accurate and fast solution in place, the
(NIDnT) port and IEEE 1149.7 standard make debug in end product packages possible. MIPI NIDnT software architecture could be optimized early
aims to bring debug, trace and test capabilities to the final product by reusing existing external in the design cycle and, in addition, the software
developer could even suggest hardware architec-
interfaces. For example, the debug interface could be shared with an external memory port such as
ture changes that would improve his SW execution
the micro SD card interface. times and even lower the power consumption of the
IEEE 1149.7 is a new debug standard which preserves industry investment while providing ad- mobile device.
ditional features. IEEE 1149.7 is on track for ratification in the first quarter of 2009. It allows debug The latter is an important design constraint and
is correlated to the activities in the processors, on the
connections with fewer pins than the IEEE 1149.1 (JTAG) standard, yet can provide additional
buses and in the peripherals. The VSP could be used
functionality. IEEE 1149.7 also provides for the transport of information through a background data to detect power trends early in the design phase.
channel, thereby increasing the utility of the two pins used. IEEE 1149.7 has features which are ben- This is simply done by weighting simulation events
eficial to embedded SoC in a wireless device context. Along with reduced pin-count requirements, with coefficients. It is possible to assign a cache miss
event with a power coefficient higher than normal
IEEE 1149.7 allows for operation in new connection topologies, making stacked die and multi-chip
cache resident execution, as the fetch over the bus
modules easier to build. It also improves on JTAG by specifying power scenarios for the debug will increase the power consumption by triggering
logic. This aids the SoC in further reducing power consumption. additional gates on the silicon. With a fast and accu-
26| wirelessdesignmag.com V i r t u a l P r o t o t y P e S i m u l at i o n
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rate VSP solution, all other contributing events could above, it is possible to setup statistic counters that Other host resources could be used as well. For
be detected and weighted, e.g., idle states of proces- measure the load and are reset when the periodic example, the host USB port within the VSP can
sors, normal execution, access to external buses, interrupt service routine is called with the start of be used to emulate the connection of the wireless
clocked down or switched off domains. each frame. These processor load analyzers are device to serial devices.
setup in a way that the operating system idle loop The above features have been used in production
VSP Benefits instructions are excluded from the load calculation. of a semiconductor vendor to develop and debug
Additional benefits of a VSP include better vis- Another example is that there are no limitations as a 3G protocol stack shipped with the silicon. The
ibility and debuggability. Once the simulation is to what further events are listed in the function VSP was hooked up to a 3G tester running on a
paused with a debugger to inspect system registers, profiling table. It is already common to list the separate PC via Ethernet. It was possible to initiate
states and signal levels, the whole simulation is function profiling table with cache statistics, bus a call and debug issues using this setup.
paused. That means that all the other compo- activities etc. And with a virtual solution, this view In Figure 2, the VSP setup for 3G modem proto-
nents are stopped. A second processor would not can be extended with hit and miss rates of the cus- col stack development illustrates the setup, and the
continue to execute code and possibly write data tomized L2 cache that is part of the SoC. software based 3G tester had an interface to provide
into shared memory locations that are currently the application processor directly with the 3G frames
debugged, or FIFOs would not fill up and hinder Using Host Resources allowing the baseband processing to be abstracted
narrowing down issues. Running the complete system as a virtual simu- away in order to further speed-up the simulation.
As with a C/C++/SystemC based VSP all objects lation on a PC also offers the capability to use
of the simulation could be accessed and traced at host resources for debugging. The target software WDD
any time. It is also possible to use high-level debug- could use print to output messages, file IO and
ging techniques − for example to find out the 3G pipes to communicate to other applications imme- Jeff Roane is vice president of marketing for VaST Systems
frame that causes the largest CPU load based on diately within the embedded target software. Those Technology Corporation, 1250 Oakmead Pkwy., Sunnyvale, CA,
the data rate chosen in the High-Speed Downlink features can be easily used; however, the drawback 408-328-3300, www.vastsystems.com.
Packet Access (HSDPA) mode. is that they are intrusive and have an impact on the Cycle-accuracy and modeling of all using case dependent details
This is easily possible as a VSP offers non- software execution time and need to be removed in is key for VSPs so that they can be used for pre-silicon software
intrusive analyzing capabilities. For the example the final production code. development.
Virtual Prototypes: the Debugging Panacea
D e s i g n TA l k
By David Kleidermacher, Chief etc.) from varying vendors. The combination of technology advancement
technology officer, Green Hills Software, and ubiquitous standards translates to a near-future world of powerful vir-
inc. In recent years, simulators designed for tual prototyping platforms that will become the de-facto choice for software
embedded software development have reached a development.
new capability level due to advances in virtualization Virtual prototypes also present the ideal debugging environment. The
technology and the speeds of host PCs. Similar tech- prototype is omniscient with respect to system operation, and the host plat-
nologies used to implement virtualization in the data center are now used form can be used to store a history of execution that enables developers
to make these “virtual prototypes” faster. This, in turn, enables software to go back at their leisure to replay complex system behavior and easily
developers to simulate more complex applications, in some cases, the same locate the source of bugs and inefficiencies. These software-centric debug-
complete system that will run on the physical hardware target. A number ging capabilities are spilling over to the hardware developer. Some virtual
of companies, including Green Hills and Synopsys, now supply these high prototype debuggers can handle the SystemC and RTL source code itself.
speed virtual prototyping environments to software developers, enabling The debugger provides hardware-language awareness (e.g. SystemC’s
them to develop and integrate software before hardware is available or ports, signals and modules), and it can debug multiple hardware contexts
when it is in short supply, saving time to market. in parallel.
Hardware model standardization is currently an area of considerable In essence, the software developer is benefiting from the hardware devel-
activity, and a key industry goal is to enable virtual prototypes to interop- oper’s appreciation of modeling while the hardware developer is benefiting
erate with models of varying implementation (RTL, System C, “native” C, from the appreciation of state-of-the-art source code debugging tools.