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Parallel Interleaved Inverters for Reactive Power and Harmonic Compensation L. Asiminoaei1, E. Aeloiza2, J. H. Kim3, P. Enjeti2, F. Blaabjerg1, L. T. Moran4, S. K. Sul3 1) 2) 3) 4) Institute of Energy Department of Electrical Engineering and Computer Department of Electrical Technology, Engineering, Science, Engineering, Aalborg University, Texas A&M University, Seoul National University, University of Concepcion, DK-9220, Aalborg SE, 77843 College Station, 151-742 Seoul, Conception, Denmark, Texas, Korea, Chile, las@iet.aau.dk, eaeloiza@ee.tamu.edu, ghks95@eepel.snu.ac.kr lmoran@udec.cl fbl@iet.aau.dk enjeti@ee.tamu.edu sulsk@plaza.snu.ac.kr Abstract − This article investigates the concept of This movement creates a potential market for high power paralleling power inverters for reactive power and harmonic reactive compensation devices, motivating the production of compensation. The investigation focuses on a topology that efficient reactive power units. Thereby, the research may be shares the dc-bus capacitor between two parallel interleaved leaned in finding new topologies with cheaper passive inverters. The advantages of the proposed approach are: i) components, higher power integration, higher redundancy decreased current ripple or use of lower switching frequency and lower EMI [9]. due to the interleaving, ii) reduced stress in dc-link capacitor due to the shared connection, iii) efficient implementation for The present work analyzes the application of parallel- high power applications because of paralleling. Different interleaved inverters for reactive and harmonic current comparisons between the selected topology and regular power compensation. The topology consists of a parallel connection converters are discussed. Practical tests, on a three-phase 5 of (two) identical three-phase interleaved PWM inverters, kVA, 400 V prototype, are presented to validate the analysis. sharing the same dc-capacitor as depicted in Fig. 1. Several issues are presented and discussed in the paper; like reduction of the switching current ripple, the use of smaller Keywords – interconnected power systems; pulse width passive components and the implementation of different modulated inverters; reactive power; power system modulation strategies to reduce the EMI. The design of the harmonic; active filters. selected topology is discussed by comparing it to regular power inverters. I. INTRODUCTION The results obtained show that for the proposed topology The demand of high power in power electronics is the line inductors are reduced almost to 60% comparing to a usually limited by the available semiconductor technology, typical there-phase PWM inverter. Furthermore, if the due to the maximum allowed current, voltage, losses and topology is to be used for reactive power compensation then switching frequency. One solution to cope with the required the dc-capacitor is reduced to 25%, due to the decrease of power is to build the power converter from multiple lower dc-current ripple. power units connected in parallel, either connecting multiple As the present technology in IGBT’s allows for power switches or multiple inverters in parallel [1]−[3]. switching frequencies typically of 10 kHz − 20 kHz, it opens This paper discusses the connection in parallel of multiple the possibility of a reactive power compensator mainly inverters. Some arguments to support the paralleling concept composed of semiconductors with very small passive are briefly described such as it is easier to extend the total components. Hence, the usage of smaller passive rated power of the application by simply adding a new components and the possibility of building it as a modular inverter. The design, production, installation and maintenance device makes this topology very attractive for high power of each inverter become much simpler and flexible. industrial applications. Furthermore, parallel inverters may be physically implemented as independent controlled modules, which give the entire power unit an intrinsic redundancy feature, providing ride-through functions when a module fails (Fig. 1). There are many parallel topologies described in the literature, for different fields especially where a high power density integration is required, such as power sources, traction systems, uninterruptible power supplies [4], power factor correction circuits and active power filters (APF) [5], [6]. Regarding the compensation of the reactive power, different considerations [7], [8] are currently discussed, proposing that the users supplying reactive power should be paid since they provide voltage regulation and reduction of Fig. 1. Principle diagram of paralleling n multiple power inverters. All the power losses. inverters share the same capacitor Cdc. Authorized licensed use limited to: Universidad de Concepcion. Downloaded on November 10, 2008 at 20:36 from IEEE Xplore. Restrictions apply. Fig. 2. Typical active front-end inverter topology Fig. 3. Diagram of 2 separated parallel inverters Fig. 4. Diagram of the analyzed topology with 2 (Case-A). with split dc-capacitors (Case-B). parallel interleaved inverters sharing the same dc- capacitor (Case-C). II. ANALYSIS AND DESIGN TABLE I. Input parameters used in design and testing (see Fig. 5). This section gives the design of the selected topology. Parameter Symbol Normalized Test values value The main focus is put on the line inductance and the dc- Inverter power Sinv 1 pu 4.8 [kVA] capacitor, which are designed based on some initial Line voltage VLL 1 pu 400 [V] considerations. The assumptions are that the design is Line current (peak) Iinv (pk) 1.42 pu 10 [Apeak] carried out initially for sinusoidal output current and then Line current (RMS) Iinv 1 pu 7 [ARMS] after the obtained design is extended for active power filters, Current ripple (peak) ∆imax 20 %Iinv (pk) 2 [Apk-pk] where the inverters control non-sinusoidal currents. Both Ratio of current ripple KIf = ∆imax/Iinv 0.28 pu 0.28 pu Base impedance Zb = VLL/ 3 Iinv 1 pu 33 [Ω] parallel inverters are running with the same switching Ratio of line inductors KLf= 2πf1Lf/Zb - - frequency, and the inverters have the same power rating, Ratio of common mode coils KLcm= 2πf1Lcm/Zb - - thus the total output power is equally divided between them. DC-voltage Vdc 1.8 pu 700 [V] Three cases are studied: Ratio of dc-voltage KVdc =Vdc/VLL 1.8 pu 1.8 pu • Case-A − single unit inverter (typical three-phase DC-voltage ripple ∆vmax 1-2 % ⋅ Vdc 10 [V] inverter as shown in Fig. 2), Line frequency f1 1 50 [Hz] Switching frequency fsw 204 10.2 [kHz] • Case-B − parallel connection of 2 interleaved inverters Ratio of switching freq. Kfsw = f1/fsw 204 204 with split dc-capacitors (as in Fig. 3), Duration of zero vector t0 - - • Case-C − parallel connection of 2 inverters, both Ratio of zero vector Kt0= t0/Tsw - - sharing the same dc-capacitor (as in Fig. 4). Several criteria are imposed, for having the same base of A. Line Inductor comparison between the selected topologies (see Fig. 5 and Table I): line-to line voltage VLL is set to 1 per unit (pu), The design of the inductor is based on the imposed line total output power Sinv of 1 pu (consequently the total current ripple, which depends on the existing dc-voltage, current delivered to the source Iinv of 1 pu), line current modulation strategy and switching frequency as used in (1). There are different methods to calculate the value of the ripple is limited to ∆imax, voltage ripple across the dc- switching current ripple as a function of the modulation capacitor is limited to ∆vmax. strategy and the desired line inductor [12]. A previous study The design is carried on along with different practical tests [13] investigates a simplified method for calculation of the on a laboratory setup described in §V. The values of the line line inductor, based on the equivalent model of the inverter inductors are 5 % (i.e. 5 mH) for Case-A and 3 % (i.e. 3 in each commutation states. The value of the line inductor Xf mH) for Case-B and -C. The total line current Iinv is 6 Apeak. for Case-A is finally obtained as in (3). di f (t ) vs (t ) = L f + vi (t ) (1) dt Vdc ⋅ ∆t K V ⋅ ∆t ∆imax = 2 = 2 Vdc LL (2) 3L f 3L f 4π KVdc VLL f 4π KVdc Z b X (f CASE − A) = ω1 L f = ⋅ ⋅ 1 = ⋅ 3K If 3Iinv f sw 3K If K fsw (3) Zb 1/ K fsw For Case-B and Case–C, the inductor is designed using the same equation as in (1) separately applied for each inverter. The total line current is the summation the individual inverter currents. Fig. 5. Imposed criteria used for designing the power inverter. Authorized licensed use limited to: Universidad de Concepcion. Downloaded on November 10, 2008 at 20:36 from IEEE Xplore. Restrictions apply. (A) (B) (C) (D) (E) (F) Fig. 6. Measured line currents for a reference current of 6 Apeak reactive current and sinusoidal PWM modulation: A) Case-A, B) Case-B, C) Case-C; D), E), F) harmonic current spectrum for each measured current focused at the switching frequencies. It is proven in [13] that the total line current ripple (Ifsum effect, since its frequency is given by the switching in Fig. 3) is reduced due to the interleaving, to a fraction of frequency. The amplitude of the cross-currents can be 0.6 times individual inverter’s ripple. Or vice versa, if the calculated as in (5). line current ripple is maintained as imposed in Table I, then Fig. 6 shows the time- respective the frequency domain the inductors can be reduced by the same amount, as given waveforms of the measured currents for all three cases. The in (4). line current ripple in Case-B and -C is near the same as the X (f Case − C ) = X (f Case − B ) = 0.6 ⋅ X (f Case − A) ripple in Case-A, even though the line inductors are (4) decreased to 60 % in Case-B and -C. The cross-current Icc When connecting the inverters in parallel, cross-currents can also be seen in Case-C. circulate from one inverter to the other, depending on the Different solutions can be found to reduce or eliminate inverters’ switching states. If the power source is stiff, (i.e. the cross-currents as like: galvanic isolation transformer [6], low short-circuit impedance), then the cross-currents in separate dc-capacitors [15], inter-phase coils on the dc-bus, Case-B are negligible, because the current ripple generated higher switching frequency PWM strategies [16]. by each inverter sinks into the grid. Most of these solutions have different drawbacks, for instance However, for Case-C, because there is no galvanic the galvanic isolation transformer must be designed for higher isolation between inverters and they share the dc-capacitor frequency and rated at the total nominal current; the inter- Cdc, there is a circulation current (referred to as cross-current phase coils must carry a dc-current which is difficult to design Icc in Fig. 6C) that occurs due to the opposite zero vectors v7 in respect the core saturation limits; the increase in the and v0 [13]. The cross-current Icc is the natural consequence switching frequency may also be limited in practice. of interleaving the carriers by 180°. The solution applied here is the use of common mode There are 2 important effects of the cross-current. The coils (Lcm in Fig. 4) to provide a high impedance path for first effect is the increase of the current peak value in each circulating cross-currents. inverter as it will described next. The second effect is the ∆icc (t ) risk that may appear in the case of a small unbalance Vdc = ( L f 1 + L f 2 + Lcm1 + Lcm 2 ) (5) t0 (t ) between inverters (e.g. different line inductances, different where: Vdc is the voltage on the dc-capacitor, the Lf1, and Lf2 are the values duty cycles), which determines a lower frequency current of the line inductors, ∆icc is the amplitude of the cross-current developed circulating between inverters as a zero-sequence current during the interval t0 which depends on the duration of the zero vectors. [14]. Since the zero-sequence current is of a low frequency, 2 3π KVdc Kt 0 VLL f1 3π KVdc K t 0 a proper controller designed for the zero-axes can remove it. I cc = = I inv 2( K Lf + K Lcm ) 3Z b f sw ( K Lf + K Lcm ) K fsw (6) However, a current controller cannot mitigate the first I inv 1/ K fsw Authorized licensed use limited to: Universidad de Concepcion. Downloaded on November 10, 2008 at 20:36 from IEEE Xplore. Restrictions apply. Fig. 7. Cross-current Icc as a function of both Fig. 8. Currents and inductances in Case-C as Fig. 9. Evaluation of the weight and volume of 2 inductances: inverter inductance Lf respective functions of the inverter power a) Line current and inductors of 3 % (Case-C) and an inductor of 5 % common mode inductance Lcm. cross-current. b) Line inductance (3 %) and (Case-A) for different values of the inverter current common mode inductance. If. As indicated in (6), the cross-current depends on the size However, as Case-C has supplementary common mode of both, line inductor (Lf) and the installed common-mode inductors, their weight and volume must also be considered. inductor (Lcm). Fig. 7 presents how the cross-current It is expected that the common-mode inductors may not be develops along with the line inductance. It can be seen that a very large since their core must be designed mainly for larger common-mode inductor can effectively reduce the common-mode signals and not the nominal inverter current. cross-current. For instance, for a value of 3 % line On the other hand the use of common-mode coils is a inductance alone, the cross current is about 0.3 pu, while common practice in industry for protecting the inverters installing an additional common-mode inductance of 3 % against common mode noise signals from the grid, thus such reduces the cross-current to near 0.1 pu. inductors are used anyway. Another calculation example of the common-mode inductor is given in Fig. 8. Here the size of the common- B. DC-link Capacitor mode inductor is selected based on the desired value of the cross-current. For a cross-current Icc of 15 % out of the total When the inverter provides only reactive current the inverter current, the common mode inductor has almost the capacitor may be sized based on the dc-voltage ripple same absolute value as the line inductor. If one designs the caused by the switching frequency. As a general approach application for lower cross-current, then the value of the the minimum required dc-capacitor is determined as: common-mode inductor should be highly increased. For an t2 allowed cross-current value of only 5 %, the common-mode ∫i dc (t ) dt , idc (t ) = sa (t ) ⋅ ia (t ) + sb (t ) ⋅ ib (t ) + sc (t ) ⋅ ic (t ) , Cdc ,min = t1 inductor is almost 3 times higher. ∆vmax (t ) (7) As previously calculated, the line inductors are reduced where idc(t) and vmax(t) are the capacitor current and voltage ripple; sa, to 60 % by interleaving the carriers, in order to keep the sb, sc are the switching functions, and ia(t), ib(t), ic(t) are the line same amplitude for the line current ripple. However, as currents. Case-A uses a single three-phase inductor, while Case-B and If some simplified assumptions are considered such that -C use two pairs, the design demands more analysis if this is the integration time interval (t1, t2) is half of the switching economically feasible. In practice, the weight, size, and cost period Tsw and the dc-current (Idc) is half of the peak value of of the inductors are of a major concern. They all depend on the nominal line current [12], then the minimum required many parameters, like the magnetic core, type of windings, dc-capacitor for Case-A is: manufacturing technology, desired tolerance and required 1 2 I inv Tsw ( Case − A) 1 1 operating conditions. These are difficult to analyze from a Cdc ,min = 2 ∆v 2 = 2 6f K ⋅ (8) simple approach, but it is assumed that the relation between max 1 dc max KVdc K fsw Z b inductors maintains the same. An evaluation is given in Fig. 9 for two types of inductors, For Case-B, the dc-current in each capacitor is half of one of 5 % (as in Case-A) and the other of 3 % (as in Case- the total line current, because of the power sharing, which B or -C). The inductors are calculated as in [17] using makes the ripple of the dc-voltage half as calculated in laminated iron core, sinusoidal line current and an operating Case-A. Or vice-versa, if the dc-voltage ripple is kept constant, then the capacitor can be reduced to half. temperature of 25 °C. The calculations did not consider the In Case-C, since the capacitor is shared between two required increase of the inductor size in order to cope with interleaved inverters, the instantaneous dc-current is half of the heat caused by the power losses in core and windings, Case-A and its frequency is doubled. This makes the thus the inductor size increases almost linear with the capacitor 4 times lower than in Case-A. current [17]. Fig. 9 shows that the weight of a 5 % inductor rated for 600 C ( Case − A) C ( Case − A) ( Case ( Case Cdc ,min− B ) = dc ,min , and Cdc ,min−C ) = dc ,min (9) Amps is higher than the weight of 2 inductors of 3 % rated 2 4 for 300 Amps each. Their volume is also in the same ratio. Authorized licensed use limited to: Universidad de Concepcion. Downloaded on November 10, 2008 at 20:36 from IEEE Xplore. Restrictions apply. If the application is an active filter, then the capacitor value Thus, the comparison between Case-A, -B, -C, resumes should be calculated to cope with a certain value of dc- to the calculation of the THDHF caused by the switching voltage drop caused by the load variation. frequency. The spectrum of the measured dc-current is VLL ∆I inv calculated for all three cases in Fig. 11. Cdc − A ) = ( Case 2 3 (Vdc , drop − Vdc ) f1 2 2 (10) For Case-A the THDHF is double compared to Case-B, but only one of the capacitors is measured in Case-B, Since where ∆Iinv is the step increase in the real fundamental line current; Vdc,drop is the maximum allowed variation of the dc-voltage. the capacitor is of a lower capacitance, the equivalent RESR is almost double, and thus the total power losses for both This means that the required capacitance is much larger capacitors together in Case-B is near the same as the value than the value in (8) [18]. For Case-B, the dc-capacitor is calculated in Case-A. In order to reduce the losses the still half of Case-A because the inverter power is half. capacitor, its capacitance must be increased but this is not However, for Case-C the dc-capacitor is the same as in economically viable. Case-A, because the same amount of power is required to be For Case-C the THDHF is half and there is only one dc- stored in dc-link in order to cope with the load variation. capacitor. This indicates that the total current stress in Case-C Another important issue when designing the capacitor is is reduced to 25 % compared to Case-A. However, if the the current stress. Different methods are proposed in capacitor is 4 times lower (i.e. RESR 4 times higher), the total literature, either spectral analysis or simulations [12]. The power losses would be the same. Therefore, the capacitor may dc-current determines specific power losses in the capacitor be selected for example only 2 times lower instead of 4 times, as in (11) and consequently an increase of the capacitor which is sufficient enough to reduce the losses to half. temperature as in (12), thus decreasing its lifetime. PCdc = ∑ ( PESR (h) ) = ∑ ( RESR (h) ⋅ I C , RMS (h) ) 2 (11) h h C. Inverter rating TCdc = Ta + PCdc ⋅ Rth (12) The rating of the inverter is determined by calculating where TCdc and Ta are the capacitor respective ambient temperatures, the IGBT currents. The cross-current changes the shape of RESR(h) and IC,RMS(h) are the equivalent series resistance respective the RMS the IGBT current with a possible increase of the switching current of the capacitor at different harmonic orders h. and conduction power losses. However, simulation of the The equivalent series resistance (RESR) decreases whenever inverter for different common mode inductors shows that one of the following increases: ambient temperature Ta, the RMS value of the IGBT current has insignificant ripple current, current frequency, capacitor can size, and changes, but only the peak value increases (see Table IV and capacitance (for the same can size) [19]. Variation of RESR Fig. 12), [13]. with the frequency is only of a small amount, and practically it can be considered constant for any frequency higher than III. CONTROL STRUCTURE 2-3 kHz. Its value is averaged to 0.45 times the RESR value The control algorithm may be developed in different for 100 Hz at 20°C (see Fig. 10a). On the other hand, the ways, either in stationary or synchronous frames. Here the variation of RESR with the capacitance is much larger, last was selected for implementation [13]. A typical control reaching a difference of almost 2 times, if one compares the diagram for Case-A is given in Fig. 13a, which has a current RESR of a given capacitor to its double value (see Fig. 10b). controller (Reg Idq) in the inner loop and a voltage controller If one splits the power losses from (11) into low order (Reg Vdc) in the outer loop. harmonics ( PCdc caused mainly by the control) and high LF For active harmonic filtering applications the load order harmonics ( PCdc caused by the switching frequency), HF current is also measured and the harmonic currents are and takes into account that the ESR is almost constant for isolated and imposed as current reference (IHRef) by the higher frequencies, then it can be proven that high frequency harmonic detection block. For Case-B, since there are 2 power losses are directly dependent on the total harmonic independent inverters, the control of each is self-regulating, distortion (THDHF) calculated as in (13). which means that the overall implementation of the control I is twice as in Fig. 13a. (h) 2 PCdc = 0.45 ⋅ RESR (100 Hz ) ⋅ I C , RMS ∑ C , RMS HF 2 h > 50 I C , RMS (13) 2 THDHF , h>50 (a) (b) Fig. 10. Excerpt from capacitor datasheets showing the dependence of ESR Fig. 11. Measured harmonic spectrum of the dc-currents for a) Case-A, b) with the frequency and capacitance [19]. Case-B at only one of the inverter, c) Case-C. Authorized licensed use limited to: Universidad de Concepcion. Downloaded on November 10, 2008 at 20:36 from IEEE Xplore. Restrictions apply. The control diagram for Case-C is particular because of The common mode inductors in Case-C are set to Lcm1= the shared dc-capacitor. Thus, there are two additional Lcm2=2 mH. Some of the measurements are already issues, the zero sequence current and the common dc- presented in §II regarding the generation of the reactive voltage regulation. power (Fig. 6). In a typical three-phase three-wire stand-alone inverter the Initially the design of the inverter in §II was done for a zero-sequence current generated by the zero vectors does not sinusoidal modulation strategy (SPWM). Other types of flow, but in the existing topology with parallel inverters there modulations are also practically tested as it can be seen in Fig. is a circulating cross-current as explained in §II. Even if the 14A: space vector modulation (SVM), discontinuous average of the cross-current theoretically is zero during one modulation with different types of switch clamping (DPWM1 fundamental period, any small difference between the and DPWM3) [12]. inverters determines a lower frequency current circulating Fig. 14B and Fig. 14C show the simulated line current ripple between them. The zero-sequence current is removed by a as power factor correction (PFC) for Case-A with a line current controller placed on zero-axis (Reg Iz), which keeps a inductor of 5 mH respective for Case-B with a line inductor of null average of the zero sequence current [14]. 3 mH each inverter. As it can be seen, the maximum value of As both inverters use the same dc-capacitor there is one the line current ripple is near the same for SPWM (and also single voltage control loop. The output of the voltage DPWM3), which validates the design. For the SVM and controller is equally divided to be the reference for both DPWM1 the ripple increases. For Case-C the line current inner current controllers. This creates a balance in the power ripple is similar for SPWM and SVM. However, losses dissipation for both inverters and also assures closer discontinuous modulations cannot be implemented [16] symmetry in the voltage references for each inverter, which because cross-currents cannot be regulated, as there are no is needed in order to have a good cancellation in the current alternative zero vectors v0 and v7 during one switching period. ripple. For the same reason the harmonic current reference is Table II indicates the losses measured of the total equally divided for each inverter. inverter in each case for all four modulation strategies. Case-C has always higher losses because of there are 2 V. EXPERIMENTAL RESULTS inverters (thus, involving switching and conduction losses) but also because of the circulation of the cross-current that All three cases are evaluated on an existing laboratory increases the losses in the line inductors. stand used for compensation of both reactive power and Fig. 15 shows the mitigation of the harmonic currents and harmonic current distortion. The setup consists of 2 paralleled the spectrum of the line current Is (see also Fig. 4), which inverters of a total power of 5 kVA, working at 10.2 kHz indicates that the switching frequency is reduced for Case-B switching frequency. The line inductors are set as Lf=5 mH and -C. Different other results are collected in Table III. for Case-A and Lf=Lf1=Lf2=3 mH for Case-B and -C. Fig. 12. Representation of the IGBT current during one commutation period. (a) (b) Fig. 13. Diagram of the control in dq-reference frame for a) Case-A, b) Case-C. TABLE II. Measured power losses of the total inverter for different modulation strategies tested on the existing setup. Losses [%] vs. Case- Case- Case- modulation A B C SPWM 3.8 5.1 6.5 Reactive SVM 4.8 3.7 5.8 power DPWM1 3.4 5.3 8.2* DPWM3 3.2 3.5 6.2* SPWM 2.8 3.4 7.1 Harmonic filtering SVM 2.6 3.1 6.6 DPWM1 2.4 3.0 8.0* (A) (B) (C) DPWM3 2.2 2.9 6.7* * Fig. 14. Simulated line current ripple for different PWM strategies. a) sin-PWM b) space vector modulation SVM, practically not viable because of the c) and d) discontinuous PWM (DPWM1,3). A) voltage reference, B) line current ripple in Case-A for Lf of 5 %, strong cross-current [16]. B) line current ripple in Case-B for Lf1, Lf2 of 3 %. Authorized licensed use limited to: Universidad de Concepcion. Downloaded on November 10, 2008 at 20:36 from IEEE Xplore. Restrictions apply. (a) (b) (c) Fig. 15. Measured waveforms for mitigation of harmonic currents generated by an Adjustable Speed Drive of 2.5 kVA a) Case-A, b) Case-B, c) Case-C. TABLE III. Comparison of the selected topologies for an inverter power [4] L. Woo-Cheol, L. Taeck-Ki, L. Sang-Hoon, K. Kyung-Hwan, H. Sinv=3 kVA and a switching frequency of 10.2 kHz. Dong-Seok, S. In-Young "A master and slave control strategy for * parallel operation of three-phase UPS systems with different Parameter Case-A Case-B Case-C ratings", Proc. of APEC '04, Vol. 1, 2004, pp. 456-462. Front line inductor value (Lf) 0.05 pu 0.03 pu 0.03 pu [5] G. Ledwich, P. Doulai, "Multiple converter performance and active DC-link capacitor value (Cdc) 0.62 pu 0.31 pu 0.15 pu filtering", IEEE Trans. on Power Electronics, Vol. 10, No. 3, pp. 273- Total power flow in each inverter (Sinv) 1.00 pu 0.50 pu 0.50 pu 279, 1995. Total line current distortion (THDi) 6.5 % 8.4 % 8.9 % [6] H. Akagi, A. Nabae, S. Atoh, "Control strategies of active power filters using multiple voltage-source converters", IEEE Trans. on Ind. 1st switching frequency harmonic of Ifsum 5.6 % 2.0 % 2.1 % App., Vol. 22, No. 3, pp. 460-465, 1986. 1st switching frequency harmonic of If1 5.6 % 7.2 % 18.2 % [7] Federal Energy Regulatory Commission web resource, Current rating for one IGBT [Arms] 0.53 pu 0.28 pu 0.29 pu “http://www.ferc.gov”, 2005. Maximum current for one IGBT [Apk] 1.15 pu 0.75 pu 0.90 pu [8] National Energy Marketers Association, web resource, * tested for a common mode inductor Lcm of 2 mH. “http://www.energymarketers.com/Documents/02-04-05-reactive- power.pdf”, 2005. [9] A.M. Kamel, T.H. Ortmeyer, "Harmonic reduction in single-phase VI. CONCLUSION inverter using a parallel operation technique", Proc. of APEC' 89, 1989, pp. 101-108. This paper discusses a parallel topology of 2 three- [10] F. Blaabjerg, Z. Chen, S.B. Kjaer, "Power electronics as efficient phase power inverters connected in parallel and sharing the interface in dispersed power generation systems", IEEE Trans. on same dc-capacitor. A comparison of the selected topology Power Electronics, Vol. 19, No. 5, pp. 1184-1194, 2004. with a regular three-phase inverter for application is [11] F.V.P. Robinson, V. Chunkag, "Parallel connection of single-switch there-phase power factor correction converters for interleaved presented for reactive power and harmonic compensation. switching", IEE Proc. of. of Electr. Power Application, Vol. 144, No. The paper gives different design specifications, which prove 6, 1997, pp. 423-433. that for the selected topology the passive components are [12] J.W. Kolar, H. Ertl, F.C. Zach, “Influence of the modulation method significantly reduced. Simulation and experimental results on the conduction and switching losses of a PWM converter system”, for a 400V/5kVA unit validates the presented analysis. IEEE Trans. on Ind. App., Vol. 27, No. 6, pp. 1063-1075, 1991. [13] L. Asiminoaei, E. Aeloiza, J.H. Kim, P. Enjeti, F. Blaabjerg, L. T. ACKNOWLEDGMENTS Moran, S.K. Sul, “An interleaved active power filter with reduced size of passive components”, Proc. of APEC’06, Vol. 1, 2006, 969 − 976. The authors want to acknowledge the financial support from Aalborg University, Aalborg, Denmark project 562/06- [14] Y. Zhihong, D. Boroyevich, C. Jae-Young, F.C. Lee, "Control of circulating current in two parallel three-phase boost rectifiers", IEEE 14-23632 and the help received from Hitachi Metals Europe, Trans. on Power Electronics, Vol. 17, No. 5, pp. 609-615, 2002. Duesseldorf, Germany regarding the magnetic materials for [15] S. Ogasawara, J. Takagaki, H. Akagi, A. Nabae, “A novel control the common mode coils. scheme of a parallel current-controlled PWM inverter”, IEEE Trans. on Ind. Appl., Vol. 28, No. 5, pp. 1023-1030, 1992. [16] K. Xing, F.C. Lee, D. Borojevic, Z. Ye, S. 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