Cryocooled Wideband Digital Channelizing RF Receiver Based on Low

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					ISEC’2007, Extended Abstract P-V01                                                                                                                                                                                             1

          Cryocooled Wideband Digital Channelizing
            RF Receiver Based on Low-Pass ADC

         Igor V. Vernik, Dmitri E. Kirichenko, Vladimir V. Dotsenko, Robert Miller, Robert J. Webber,
              Pavel Shevchenko, Andrei Talalaevskii, Deepnarayan Gupta, and Oleg A. Mukhanov

   Abstract— We have demonstrated a digital receiver                                                                                                                                      PC
performing direct digitization of radio frequency signals over a
wide frequency range from kilohertz to gigahertz. The complete                                                                                             temperature
system, consisting of a cryopackaged superconductor All-Digital
Receiver (ADR) chip followed by room-temperature interface
electronics and a field programmable gate array (FPGA) based
post-processing module, has been developed. The ADR chip                                                                                                 output amplifiers
comprises a low-pass delta modulator with phase modulation–
demodulation architecture together with digital in-phase and                                                                                         current source
quadrature mixer and a pair of digital decimation filters. The
chip is fabricated using a 4.5 kA/cm2 process and is cryopackaged
                                                                                                                                                     chip mounted
using a commercial-off-the-shelf cryocooler. Experimental results
in HF, VHF, UHF and L bands and their analysis proving                                                                                               on cold head
consistent operation of the cryopackaged ADR chip up to 24.32
GHz clock frequency, are presented and discussed. To our
knowledge this is the fastest digital receiver demonstrated to date.          Fig. 1. The complete 19” rack with all components of digital receiver packaged
                                                                              on Sumitomo cryocooler.
   Index Terms— Digital receiver, superconductor, analog-to-                  The cryocooler was selected due to its relative compactness,
digital converter, SINAD, SFDR, RSFQ, cryocooler.
                                                                              adequate heat lift and air-cooled compressor. It includes a
                                                                              helium damper to reduce temperature oscillations and,

H     YPRES is developing a class of digital receivers with
      direct digitization at radio frequency (RF) for military
and commercial applications. In what follows, we describe our
                                                                              therefore, improve circuit operational bias margins. A second
                                                                              generation cryopackage with a completely redesigned 4K
                                                                              stage for better grounding and magnetic shielding provides
progress in building such a receiver for HF, VHF, UHF and L                   significantly reduced flux trapping and high thermal and
bands as a complete turnkey system. This complete system,                     electrical reliability. These improvements allow the system to
fitting in a standard 19’’ rack shown in Fig. 1, consists of an               operate with high reproducibility at clock frequencies up to
All-Digital Receiver (ADR) chip cryopackaged on a                             24.32 GHz with identical bias settings at temperatures from
commercial-off-the-shelf (COTS) cryocooler, a computer                        4.03 K to 4.38 K.
controlled multi-channel current source to bias the ADR chip,                                                 0                                                                      0
room-temperature interface amplifiers, and a PCI FPGA based                                                                         I channel
                                                                                                                                                           Normalized power (dBc)

                                                                                                                                                                                                       Q channel
                                                                                   Normalized power (dBc)

post processing module. Details of the ADR chip architecture                                                -50                 SINAD =74.6dB
                                                                                                                                                                                    -50                SINAD=74.6dB
and design are described elsewhere [1]. The single-bit                                                                          SFDR=86.1dB
                                                                                                                                16384-point FFT
                                                                                                                                                                                                       16384-point FFT
oversampled data from a low pass phase-modulation-                                                          -100                                                          -100

demodulation (LP PMD) delta modulator are applied to a
                                                                                                            -150                                                          -150
digital channelizer comprising a single-bit digital in-phase and                                                   0 Normalized frequency f/fd     0.5                                    0    Normalized frequency f/fd 0.5
quadrature (I&Q) mixer and a pair of digital decimation                                                       0
                                                                                   Normalized power (dBc)

                                                                                                                                                 Full spectrum
filters. The complete 1cm X 1 cm ADR chip contains about
10,500 Josephson junctions and was fabricated with the 4.5
kA/cm2 HYPRES process. The ADR chip is packaged on a                                                        -100
COTS Sumitomo SRDK-101D-A11 two-stage cryocooler.

                                                                                                                   0                                     ±fd/2                                                          0
Authors are with HYPRES, Inc., 175 Clearbrook Road, Elmsford, NY 10523                                                                  Normalized Frequency (f/fd)
USA (Phone: 914-592-1190; E-mail: vernik@
                                                                              Fig. 2. Spectrum of the digital I and Q data and complex I+jQ FFT for a single
This work was supported in part by the US Army and Air Force under contract
                                                                              10 MHz tone input sampled at 24.32 GHz clock, digitally filtered, and
# W15P7T-04-C-K605 and Navy under contract # N00014-03-C-0370.
                                                                              acquired to FPGA at 95 MS/s.
ISEC’2007, Extended Abstract P-V01                                                                                                                                                                                                                            2

                                                               22                                                                                                                                       50

                                                                                                                                       ADC at 20 GHz
                                                                                                                                       ADR at 24.32 GHz
                                                                                                                                       ADR at 24.32 GHz                                                 40
                                                                                                                                       (+ 1ENOB)
                                            SNR Bits (ENOBs)   16

                                                                                                                                                                                          SINAD (dBc)
                                                               14                                                                                                                                       30


                                                               10                                                                                                                                       20

                                                                     5                       6                                              7
                                                                    10                      10                                             10                     10
                                                                                    Instantaneous Bandwidth (Hz)                                                                                        10
                                                                                                                                                                                                             0.1    Input (GHz)         1       1.6
Fig. 3. ENOB vs. instantaneous bandwidth for ADR and ADC.
                                                                                                                                                                              Fig. 5. SINAD vs. input signal frequency. See text for details. Line with the
   We performed complete evaluation of the system both with                                                                                                                   slope of 3 dB/octave is also shown.
and without applying a local oscillator (LO) input. Digital                                                                                                                      Fig. 4 shows the FFT for I and Q channels and complex
outputs were acquired and displayed with the help of room-                                                                                                                    (I+jQ) FFT (16384 points) with a 1.5 GHz sinewave input. A
temperature interface amplifiers, a PCI FPGA data acquisition                                                                                                                 local oscillator at 1.49 GHz was applied. The IF at 10 MHz is
and processing board run by a custom developed graphical                                                                                                                      clearly visible for both I and Q channels. The image rejection
user interface (GUI). Fig. 2 shows the FFT for I and Q                                                                                                                        was measured from the complex FFT to be 53 dB. The signal-
channels and complex (I+jQ) FFT (16384 points) from the                                                                                                                       to-noise ratio for the 1.5 GHz input (Fig. 4) is expectedly
acquired I and Q data with a single 10 MHz tone input. The                                                                                                                    lower than for 10 MHz input (Fig. 2). This is due to the lower
full spectrum represents a bandwidth of fd = fclk /256 =95                                                                                                                    input amplitude to stay within the LP PMD ADC slew-rate
MHz. The measured SINAD of 74.6 dB over a bandwidth of                                                                                                                        limit - the maximum signal at 1.5 GHz is about 43.5 dB less
47.5 MHz compares well with 75.7 dB over a bandwidth of 39                                                                                                                    than that at 10 MHz. Additionally, the signal-to-noise ratio is
MHz produced by an LP ADC [2] with 2-channel                                                                                                                                  reduced by 3 dB further by the mixing of out-of-band
synchronizer.                                                                                                                                                                 quantization noise with the harmonics of the single-bit square-
   The single tone measurements with 2, 5, 20, and 50 MHz                                                                                                                     wave LO. With this type of LO only odd harmonics are
tones were performed with a variety of appropriate band pass                                                                                                                  present. Under the assumption that their power decreases as
or low pass filters depending on their availability. To take full                                                                                                             1/f 2 and the quantization noise power increases approximately
advantage of oversampling in our ADR, additional post-                                                                                                                        as f 2 (since the mixing occurs right after the delta modulator)
process filtering in software in the band from 0 to the tone                                                                                                                  the harmonic excess noise is approximately 4.8 dB. This
frequency was performed to remove higher frequency                                                                                                                            corresponds to 3 odd harmonics of the local oscillator that fall
components. Fig. 3 shows these data, together with our earlier                                                                                                                within the unfiltered quantization noise band 0 – fclk/2. Fig. 5
data for ADC collected at 20 GHz clock [2]. The curves (solid                                                                                                                 shows the collection with the input signal in HF, VHF, UHF
for ADC [2] and dashed for ADR investigated here) closely                                                                                                                     and L bands was applied while the LO was chosen to obtain
follow the ENOB versus bandwidth trade off curve at a rate of                                                                                                                 10 MHz IF response. The line with the slope of 3 dB/octave to
1.5-bit/octave characteristic for ideal delta modulators. To                                                                                                                  account for the 6 dB/octave loss due to the slew-rate limit and
account for the 1-bit difference in the resolution - this ADR                                                                                                                 gain of 3 dB/octave due to decrease of number of LO
chip [1] has a 1-channel vs. a 2-channel synchronizer in the                                                                                                                  harmonics within 0 – fclk/2 band is shown in Fig. 5.
20-GHz ADC chip [2] - we have plotted another set of points                                                                                                                      In conclusion, we have developed a digital receiver for HF,
by adding 1 ENOB to the ADR results.                                                                                                                                          VHF, UHF and L bands as a complete turnkey demonstrator
                                        0                                                                                        0
                                                                           I channel                                                                Q channel                 system. The system fits in a standard 19” rack and consists of
               Normalized power (dBc)

                                                                                                        Normalized power (dBc)

                                        -20                                SINAD =28 dB
                                                                                                                                 -20                SINAD =28.1 dB
                                                                                                                                                    ENOBs=4.38                a superconducting chip packaged on a COTS cryocooler and
                                                                           SFDR=30.2 dB
                                                                                                                                                    SFDR=30.3 dB
                                        -40                                16384-point FFT                                       -40
                                                                                                                                                    16384-point FFT           accompanied by all necessary custom-built room temperature
                                        -60                                                                                      -60                                          hardware and software such as a computer-controlled multi-
                                        -80                                                                                      -80                                          channel current source, interface amplifiers, a FPGA-based
                                                     0          Normalized frequency f/fd
                                                                                                                                       0    Normalized frequency f/fd   0.5
                                                                                                                                                                              post-processing PCI module, and PC with GUI. The system
                                                                                             Full spectrum                                                                    reliably operated at 24.32 GHz clock frequency with
           Normalized power (dBc)

                                        -20                                                 SINAD =28 dB                                                                      consistent performance both inside and outside of our lab run
                                                                         Image              SFDR=30.2 dB                                   Signal                             by both HYPRES and customer personnel. To our knowledge

                                                                                                                                                                              this is the fastest digital receiver demonstrated to date.

                                                                                                                                                                              [1]   D. Gupta, et al., “Digital channelizing radio frequency (RF) receiver,”
                                            0                                                                                                                           0
                                                                                    Normalized Frequency (f/fd)                                                                     IEEE Trans. Appl. Supercon., June 2007, to be published.
Fig. 4. The 16384-point spectra of the I-channel output (top left), the Q-                                                                                                    [2]   I. V. Vernik, et al., “Superconducting high-resolution low-pass analog-
channel output (top right) along with the full spectrum (I+jQ, bottom) acquired                                                                                                     to-digital converters,” IEEE Trans. Appl. Supercon., June 2007, to be
at 24.32 GHz. The input tone frequency is 1.5 GHz and the LO is 1.49 GHz.                                                                                                           published.
The output bandwidth (fd=fclk/256) is 95 MHz.