2001 Fall EE 678 Digital Integrated Circuits

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					2003 Fall
                                EE 678 Digital Integrated Circuits

Overview: This course aims to get the students exposed to the important issues in high performance
CMOS circuit design. This course also covers the data path design in full custom design methodology,
clocking strategy, and the state-of-the art CMOS logic styles. Students are required to run SPICE
simulations and do a few large sized homework assignments.


Lecture:        Time : Monday, Wednesday         10:30 ~ 11:50 am
               Place : LG Hall Auditorium
               By : Lee-Sup Kim (lskim@ee.kaist.ac.kr) (Tel. 3460 CHiPS Room 117)


Text :       Digital Integrated Circuits : A Design Perspective, 2nd Edition by Jan M. Rabaey,    Anathana
             Chandrakasan, Borivoje Nikolic.


TAs :       Kwang-Il Oh (Tel. 4443) and Byung-Gook Kim         (Tel. 4441)


Homework : Exercises in the Text (one problem set in every two weeks)


Grade :          Attendance : 10 %
                Homework :      30 %
                Term Project : 25 % (each student writes and presents a report describing his/her own
                                       new digital circuit idea, and professor and class audience evaluate
                                       the report and the presentation respectively)
                 Final Exam : 35 % (No midterm)


Class Homepage :      http://mvlsi.kaist.ac.kr
Class schedule :


Week           Date                               Topics to be covered

1        9/1          Ch.1 Introduction
         9/3          Ch. 2 The manufacturing Process
2        9/8          Ch. 3 The Devices

3        9/15         Ch. 3 The Devices
         9/17
4        9/22         Ch. 4 The Wire
         9/24
5        9/29         Ch. 5 The CMOS Inverter
         10/1
6        10/6         Ch. 5 The CMOS Inverter
                      Ch. 6 Designing Combinational Logic Gates in CMOS
7        10/13        Ch 6 Designing Combinational Logic Gates in CMOS
         10/15        Ch. 7 Designing Sequential Logic Circuits
8        10/20        Ch. 7 Designing Sequential Logic Circuits
         10/22        Ch. 8. Implementation Strategies for Digital ICs
9        10/27        Ch. 9 Coping with Interconnect
         10/29
10       11/3         Ch. 10 Timing Issues in Digital Circuits
         11/5
11       11/10        Ch. 11 Designing Arithmetic Building Blocks
         11/12
12       11/17        Ch. 11 Designing Arithmetic Building Blocks
         11/19        Ch. 12 Designing Memory and Array Structures
13       11/24        Ch. 12 Designing Memory and Array Structures
         11/26
14       12/1         Term Project Presentation (I)
         12/3
15       12/8         Term Project Presentation (II)
         12/10
16       12/15        Final Exam

				
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