CS 2200 End Week 2 Assessment

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					CS 2200 Fall 2003 Test 1 Key Key Key Key Key Key Key Key Key
Name:___________________GT Number: gt_______Sec:_____
Please indicate your GT number in the grid below so we have some chance of being able to read it. g t 0 1 2 3 4 5 6 7 8 9 0 e g 0 1 2 3 4 5 6 7 8 9 0 0 1 2 3 4 5 6 7 8 9 0 0 1 2 3 4 5 6 7 8 9 0 a b c d e f g h i j k l m n o p q r s t u v w Problem 1 2 3 4 5 6 Total Points 15 18 20 16 16 15 100 Lost Gained Running Total

x

y TA

z

You may ask TA's for clarification but you are ultimately responsible for the answer you write on the paper. Illegible answers are wrong answers. Good luck! 0. (0 points) Whose record does Greg Maddux have a chance of beating? ___ Cyrus Vance ___ Cyrus McCormack _X_ Cy Young (and he already did it!) ___ Sigh. Greg Maddux is a pitcher for the Atlanta Braves baseball team.

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CS 2200 Fall 2003 Test 1 Key Key Key Key Key Key Key Key Key
Name:___________________GT Number: gt_______Sec:_____
1) (15 points) Explain how you could reduce the number of states for IFETCH from 4 states to 3 states for the single bus design.

Ifetch 1 DrPC LdA LdMAR Ifetch2 DrMem LdIR Ifetch3 ALU func = 11 = A + 1 DrALU LcPC +15 Correct answer -3 for minor errors +5 conceptual understanding but bad implementation -15 Modification of the datapath

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CS 2200 Fall 2003 Test 1 Key Key Key Key Key Key Key Key Key
Name:___________________GT Number: gt_______Sec:_____
2) (18 points) We know by looking at the instruction set architecture for the LC2200 that certain datapath elements are defined. Items such as the PC, general purpose registers and ALU are either specified directly or may be inferred (e.g. something must do the addition). There are a number of other elements in the datapath that aren't even hinted at by the ISA. These include items such as the A and B registers, Memory Address Register (MAR) etc. Explain why these elements are needed: (Note: A vague answer such as, "There is a single bus." is not sufficient.) Tri-state buffers (drivePC, driveALU, etc.) These elements allow a functional unit to place its value on the bus or act like they are not connected. If two or more elements were to be connected to the bus at the same time they could actually cause physical damage to the electronic components. A and B registers Since we only have one bus and the ALU requires two inputs from the bus as well as one output to the bus we must somehow buffer two of the three values. The A and B registers fill this need. MAR Similar to the ALU, the memory unit (on write) needs two values so we buffer one in the MAR. Also on reads, the bus already carries the address so the data cannot be placed on the bus by the memory. IR The control logic needs to use various values out of the instruction (offset, opcode, register numbers, etc.) So the instruction must be placed somewhere to allow reference to these fields during the course of execution of the instruction. Sign extend The offset value in the instruction is a 20 bit 2’s complement value. If the 20 bit number were to be used in a 32 bit ALU a negative number would need to be sign-extended to appear as a 32-bit negative value to the ALU.

=0? and Z These elements are used to detect if the bus is zero and to store that answer for later use. They are used by the BEQ instruction. The ALU is set to subtract the two register operand values and the control logic uses the stored value later to branch or not. criteria +3 each

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CS 2200 Fall 2003 Test 1 Key Key Key Key Key Key Key Key Key
Name:___________________GT Number: gt_______Sec:_____
3) (20 points) Given the LC-2200 Single Bus Datapath implement the control sequence for load and store instructions, enumerating the control signals needed in each state combine states when possible. Use the following syntax: StateName ControlSignal1 ControlSignal2 ControlSignal3 if (opcode = x etc.) Go to StateName1 StateName ... Note: Only list the control signals that are asserted. Ifetch 1 DrPC LdA LdMAR Ifetch2 DrMem LdIR Ifetch3 ALU func = 11 = A + 1 DrALU LcPC If (opcode == "LOAD" OR opcode == "STORE") go to LOADSTOR1 LOADSTOR1: DrReg RegNo = RA LdA LOADSTOR2: DrOff LdB

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CS 2200 Fall 2003 Test 1 Key Key Key Key Key Key Key Key Key
Name:___________________GT Number: gt_______Sec:_____
LOADSTOR3: ALU = 00 = add DrALU LdMAR if(opcode = "LOAD") goto LOAD4 if(opcode = "STORE") goto STORE4 LOAD4: DrMem RegNo = RB WrReg go to IFetch1 STORE4: DrReg Reg# = RB WrMem go to IFetch2

Each state is worth approx 4 points (LOADSTOR1-3 & LOAD4 & STORE4) So,1 point off for each missing/incorrect signal; -5 for not combining states.

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CS 2200 Fall 2003 Test 1 Key Key Key Key Key Key Key Key Key
Name:___________________GT Number: gt_______Sec:_____
4) (16 points) We are going to modify the LC-2200 datapath adding a 1-bit register thusly: _________ ________ \ \ / / \ \ / / \ \_______/ / \ / \ / \ ALU / \_________________/ | | +--------------------+ | Sign | | To +------------+ N Register +------------> | Bit | | control | +--------------------+ | | | LdN----+ ___|___ \ / \ /----- DrALU \ / V | | -----------+------------- Bus This will allow us to store the sign of the ALU result by asserting the LdN signal thus latching the value of the sign bit into register N. The value of this "N register" will be available to the control logic. Using this modified datapath implement the Set-on-less-than instruction: (i.e. use the same format as used in problem 3.) SLT r1, r2, r3 # This is an R type instruction # if(r2 < r3) r1 = 1 # else r1 = 0

For the instruction format use A and B for r2 and r3 and D for r1.

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CS 2200 Fall 2003 Test 1 Key Key Key Key Key Key Key Key Key
Name:___________________GT Number: gt_______Sec:_____
Following Ifetch3... SLT1: regNo = RA DrREG LdA SLT2: regNo = RB DrReg LbB SLT3: ALU func = 10 = A - B LdN SLT4: RegNo = 0 DrReg LdA LdB if ( N == 0) go to SLT6: if ( N == 1) go to SLT5: SLT5: ALU func = 11 = A + 1 DrALU regno = RD WrReg go to IFetch1 SLT6: ALU Func = 00 = add DrALU WrReg regno = RD go to IFetch1: +4 Subtracting (i.e. A-B) +4 latching result into N +4 Branching based on N +4 Setting reg D to 1 or 0 Cannot drive N to bus.

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CS 2200 Fall 2003 Test 1 Key Key Key Key Key Key Key Key Key
Name:___________________GT Number: gt_______Sec:_____
5) (16 points) The set-on-less-than instruction in problem 4 can also be simulated using the original LC-2200 instruction set. Assume that a typical simulation would require 60 clock cycles. Furthermore, assume that the hardware implementation of the SLT instruction from problem 4 takes 10 clock cycles. (Note: Do not assume that the value of 10 clock cycles in is the correct answer for problem 4!) Assume a program will execute 1,000,000 instructions and the clock cycle time is 2 ns. The instruction breakdown will be: Instruction Type R type (excluding SLT) LW/SW BEQ SLT Pct 40% 36% 18% 6% CPI 7 8 10 10

Note: This is the instruction breakdown if the program is written using the SLT instruction. You have been asked to evaluate two alternatives: 1. Modify the datapath as in problem 5 adding additional hardware to implement the SLT instruction. 2. Use software simulation of the SLT as discussed above. How long will the 1,000,000 instruction program take to execute for each of the above scenarios? How much faster is the SLT implementation? Solution: With SLT 400,000 * 7 = 2,800,000 360,000 * 8 = 2,880,000 180,000 * 10 = 1,800,000 60,000 * 10 = 600,000 ----------------------8,080,000 cycles * 2 ns/ cycle = 16.2 ms Without SLT 400,000 * 7 = 2,800,000 360,000 * 8 = 2,880,000 180,000 * 10 = 1,800,000 3,600,000 (60 vs 10 cycles i.e. 6 times as many) 11,080,000 cycles * 2 ns/cycle = 22.2 ms

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CS 2200 Fall 2003 Test 1 Key Key Key Key Key Key Key Key Key
Name:___________________GT Number: gt_______Sec:_____
SLT Faster by 22.2/16.2 = 1.37 times as fast with slt +6 (Correct concept, setup etc. +4, correct answer +2) without slt +6 (Correct concept, setup etc. +4, correct answer +2) speedup +4 (Correct concept, setup etc. +3, correct answer +1) Accept 6 ms for answer to how much faster.

Just for info here is a way that one could implement SLT without SLT SLT R1, R2, R3 NAND ADDI ADD LW NAND BEQ ADD BEQ less: ADDI done: Mask: .word NAND ADDI ADD LW NAND BEQ ADD BEQ ADDI 7 7 7 8 7 10 7 10 7 63 53 $AT, R3, R3 $AT, $AT, 1 $AT, R2, $AT R1, Mask($zero) R1, R1, $AT R1, $zero, less R1, $zero, 0 $zero, $zero, done R1, $zero, 1 0x80000000 # # # # # # # # # Put Complement of R3 into $AT Add 1 (R3 now contains -R3) $AT = R2 - R3 Set high order bit of R1 Mask off 31 low order bits zero result means R2 < R3 Set to zero if R2 >= R3 skip over next instruction Set to one if R2 < R3

(R2 >= R3) " (R2 < R3) cycles if R2 >= R3 cycles if R2 < R3

Call it 60 cycles for easy computation.

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CS 2200 Fall 2003 Test 1 Key Key Key Key Key Key Key Key Key
Name:___________________GT Number: gt_______Sec:_____
6. (15 points) Consider a non-pipelined processor in which each instruction takes 7 ns (fetch plus decode plus execute). We would like to pipeline the implementation with stages that do EQUAL amounts of work such that the processor completes 1 instruction every 2 ns or less. How many stages do you need in the pipelined implementation? Ignore hazards.

1 2 3 4

stage stages stages stages

7 ns 3.5 2.33 1.75 <------ Solution (i.e. 4 stages)

4 stages = +15

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