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Document Sample
Issues in Integrated Circuit
Design for UHF RFID
Zhihua WANG,Xuguang SUN,
Chun ZHANG,Yongming LI
Institute of Microelectronics, Tsinghua
University,Beijing,100084,P.R.China
RFIT2007-IEEE International Workshop on Radio-
Frequency Integration Technology, pp.322-328
Dec.9-11,2007,Singapore
Advisor: Yens ho
Reporter: C.C.Lan
Outline
Introuction
Issues in Tag
Issues in Reader
Design Instances
Conclusion
RFIC Recognition and fulfillment Lab C.C.Lan 2
Introduction
۞Bar code
۞Disadvantage-
۞Lack of programmability
۞Limited storage capacity
۞In sight operation distance and low data throughput
۞RFID system
۞Consists of
۞A reader
۞Several tags
RFIC Recognition and fulfillment Lab C.C.Lan 3
Issues in Tag
• Low Power Design
• Rectifier Design
• Anti-collision Mechanism
• Security Mechanism
• On-chip Antenna
RFIC Recognition and fulfillment Lab C.C.Lan 4
Low Power Design
• Digital:
– Lower the supply voltage
• 1.5V supply voltage in 0.5 m CMOS process
• 1.14V supply voltage in 0.18 m CMOS process
• 0.6V supply voltage in 0.18 m CMOS process
– Lower the clock frequency
• Clock separation technique(3.35~3.75MHz clock
for PIE decoding)
• Digital clock manager(1MHz to produce a
synchronous 40KHz clock with Manchester-coded)
RFIC Recognition and fulfillment Lab C.C.Lan 5
Low Power Design
• Analog:
– Voltage regulator
• Perform well as the input RF power varies more than
30dB
• Design regulator into two stages( near field, far field)
– On-chip oscillator
• Ring oscillator
• Current starve ring oscillator
• Low voltage current mirrors
RFIC Recognition and fulfillment Lab C.C.Lan 6
Rectifier Design
VP
VDD
M1 M3
VL VH
to
ant. M2 M4
Vss
Basic doubler
VP
RFIC Recognition and fulfillment Lab C.C.Lan 7
Rectifier Design
CINF DC +
PMOS
IN MP1 MPb
CPr Cbp Rb
Rb Mnb
Cbn
ferroelectric
capacitor
DC -
IVC(Internal Vth cancellation)
RFIC Recognition and fulfillment Lab C.C.Lan 8
Anti-collision Mechanism
• Aloha based protocol
• To reduce the collision probability by separating
tag transmission in distinct time slot
• Key research- to optimize the slot number
• Tree based protocol
– Use a group splitting mechanism
• Disadvantage is the relatively long identification
delay
• Adaptive binary splitting protocol
– Improve to shorten identification time
RFIC Recognition and fulfillment Lab C.C.Lan 9
Security Mechanism
• Authentication
– Mutual three-pass authentication
• Encryption
– A low power encryption hardware using TEA
algorithm
– SHA-1 algorithm
RFIC Recognition and fulfillment Lab C.C.Lan 10
On-Chip Antenna
• In some applications, where the operation
distance is a primary consideration
• OCA can be an effective way to cut down
the total cost and make the size of tag
small
RFIC Recognition and fulfillment Lab C.C.Lan 11
Issues in Reader
• Carrier Leakage Problem
• CMOS PA design
RFIC Recognition and fulfillment Lab C.C.Lan 12
Carrier Leakage Problem
I-Mixer
I-IF Out
Mode Selection
(LBT or Talk) I-IF Amp
Low-Noise Amplifier
I-Buffer
Rx-In 12 dB
Switchable I-LO
Attenuator Q-LO
Stage 1 (S-to-D)
Q-Buffer
Q-IF Amp
Bias Circuit
Q-IF Out
Q-Mixer
RFIC Recognition and fulfillment Lab C.C.Lan 13
Carrier Leakage Problem
Diff
Leak2 Amplifier
Coupler
RF IN To IQ mixers
Leak Total
Tx Canceller
Leak1
VGA
Amplitude
Tuning
Phase Tuning
(fine)
Phase Tuning
(coarse) 45 deg
Selection
VCO
Tx Output
Leakage Canceller
PA DA
From IQ Mixers
RFIC Recognition and fulfillment Lab C.C.Lan 14
Carrier Leakage Problem
Tx=30dBm
RFID Tag Tx PA
“0” “1” Tx Leakage
IPA
Backscattered from RFID Tag BR-LNA
Linear
QPA
LNA
non-linear
Blocker Rejecting LNA
RSSI RSSI
Limiter
Control Unit
RFIC Recognition and fulfillment Lab C.C.Lan 15
Design Instances
• A passive RFID Tag with Standard
EEPROM
• A security Module using XTEA Algorithm
• A Single Chip RFID Reader Transceiver
RFIC Recognition and fulfillment Lab C.C.Lan 16
A passive RFID Tag with Standard
EEPROM
ANT
Voltage
RF rectifier Voltage Regulator
limiter
Demodulator
Reset
Clock EEPROM
Extraction
Logic
Charge Control
Pump
Modulation
Generator
RFIC Recognition and fulfillment Lab C.C.Lan 17
A passive RFID Tag with Standard
EEPROM
ANT
C1 C3 C5
M1 C2 C4 C6
Modulation Signal
RFIC Recognition and fulfillment Lab C.C.Lan 18
A passive RFID Tag with Standard
EEPROM
VDD_unreg
Ref
VDD_reg
Voltage LDO Voltage
Limiter Regulator
GND
RFIC Recognition and fulfillment Lab C.C.Lan 19
A security Module using XTEA
Algorithm Deltai-1
SUM SubkeyiA
<<4
SUM XOR SUM XOR
>>5
Deltai
SUM SubkeyiB
<<4
SUM XOR SUM XOR
>>5
RFIC Recognition and fulfillment Lab C.C.Lan 20
A Single Chip RFID Reader
Transceiver
off-chip cap
I-BB
ADC
I-Rx
I-LO VGA Data
Demod
Rx
PLL
900
Demod
Q-LO off-chip cap Q-Rx
Q-BB
Data
ADC
VGA
Tx
Mod
LO
PA Tx Data
RFIC Recognition and fulfillment Lab C.C.Lan 21
A Single Chip RFID Reader
Transceiver
VDD VDD VDD
L4 L3 L1
C2 TL0
L2
Rf
C1
Cf M2
Rload
C5 C4 C3
L5
M4 M3 M1
Vin
Vg3 Vg2 Vg1
RFIC Recognition and fulfillment Lab C.C.Lan 22
Conclusion
• looks into the UHF RFID IC design in
which both tag and reader have their own
design challenges
• Issues in RFID
– Low power, energy harvesting, anti-collision,
security, and OCA in tag design
– Carrier leakage and CMOS PA in reader
RFIC Recognition and fulfillment Lab C.C.Lan 23
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