# Synchronous circuit design and analysis by she20208

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```									Synchronous circuit
design and analysis
Synchronous circuit design
• To implement a synchronous circuit
corresponding to a given specification

• Revision of Yr 2 notes (copy on web)
• Wakerly 7.4
Design procedure
1.    Construct state diagram - state table
2.    State minimisation (optional)
3.    Choose state variables - State assignment
4.    Assigned state table
5.    Choose flip-flop type
6.    Determine f/f input values (excitation table)
7.    Derive f/f input equations
8.    Derive output equations
9.    Implement (required component types, initialisation …)
10.   Verify operation and performance
State minimisation
• Once a state diagram/table has been constructed,
the number of states is fixed – however, the
designer may have constructed a diagram in which
some states are equivalent and hence redundant…

• If the number of states can be reduced –
- the number of flipflops may be reduced
- the number of don’t-cares in the state table may
be increased
Equivalence…
• Two states are equivalent if they have the same
next states and outputs
(and are not ‘not equivalent’…)

• This may not always be obvious by examination
and a systematic technique uses an ‘Implication
Chart’
Implication chart
• Consider Wakerly Fig 7-51

S    00   01   11   10   Z

S1   S2   S2   S3   S3   0

S2   S4   S4   S3   S3   0

S3   S2   S2   S5   S5   0

S4   S4   S4   S7   S3   1

S5   S2   S6   S5   S5   1

S6   S4   S4   S7   S3   1

S7   S2   S6   S5   S5   1
Implication chart (2)
S1
S   00
S2
01
S2
11
S3
10
S3
Z
0
• To construct the chart we
S2      S4    S4   S3   S3   0      derive all non-equivalent
S3      S2    S2   S5   S5   0
S4      S4    S4   S7   S3   1      (incompatible) pairs of states
S5      S2    S6   S5   S5   1
S6      S4    S4   S7   S3   1

S2              S7      S2    S6   S5   S5   1       - Mark (X) any state pairs
S3
which have different o/p
values
S4   X    X    X

S5   X    X    X
- Mark () any pairs which
S6   X    X    X                                    are identical (4,6) (5,7)
S7   X    X    X                   
- Complete the chart by…
S1   S2   S3        S4        S5        S6
Implication chart (3)
S    00    01      11      10         Z
- Complete the chart by
S1   S2    S2      S3      S3         0
S2   S4    S4      S3      S3         0                     considering each remaining
S3   S2    S2      S5      S5         0
pair and entering the
S4   S4    S4      S7      S3         1
S5   S2    S6      S5      S5         1                     necessary equivalent pairs
S6   S4    S4      S7      S3         1
S2,S4                 S7   S2    S6      S5      S5         1
S2
X                                                                               eg, for S1 to be equivalent to
S3,S5   S2,S4 S3,S5
S3
X          X
S2, we require that S2S4
S4    X          X         X
As this is not true, S1 and S2
S2,S4 S4,S6
are not equivalent …
S5    X          X         X    S7,S3 S3,S5
X
S2,S4 S4,S6
S6    X          X         X                      S7,S3 S3,S5
X
S2,S4 S4,S6                          S2,S4 S4,S6
S7    X          X         X    S7,S3 S3,S5
              S7,S3 S3,S5
X                                   X

S1         S2        S3        S4                S5                S6
Implication chart (4)
• In this example, S4S6 and S5S7
– reducing 7 states to 5

S    00   01   11   10   Z
S   00   01   11   10   Z
S1   S2   S2   S3   S3   0
S1   S2   S2   S3   S3   0
S2   S4   S4   S3   S3   0
S2   S4   S4   S3   S3   0
S3
S4
S2
S4
S2
S4
S5
S7
S5
S3
0
1
    S3
S4
S2
S4
S2
S4
S5
S5
S5
S3
0
1
S5   S2   S6   S5   S5   1
S5   S2   S4   S5   S5   1
S6   S4   S4   S7   S3   1
S7   S2   S6   S5   S5   1

• Note that equivalence is transitive, so if AB and BC then AB C
• This method can also be extended to incompletely-specified tables,
containing don’t-care terms…
State assignment
• The minimum number of flip-flops needed to
encode N states is log2N
• There are many possible assignments of binary
codes to states, each leading to a different
circuit…
• The state assignment problem is to choose an
‘optimum’ assignment (typically leading to a
minimum-cost circuit)
State assignment (2)
• In practice, a ‘good’ state assignment is found
using rules-of thumb, for example –

1. If two or more states have the same next state,
they should be given adjacent assignments

2. If two states are both next states of a present
state, they should be given adjacent assignments
State assignment (3)
S     00    01   11    10      Z

• Consider Table 7.6             S1    S2    S2   S3    S3      0
S2    S4    S4   S3    S3      0
S3    S2    S2   S5    S5      0
S4    S4    S4   S5    S3      1
S5    S2    S4   S5    S5      1

•   From Rule 1                       From Rule 2
Next state    reached from        Present state            reaches
1          -                      1                     2, 3
2          1, 3, 5                2                     3, 4
3          1, 2, 4                3                     2, 5
4          2, 4, 5                4                     3, 4, 5
5          3, 4, 5                5                     2, 4, 5

Cant satisfy all these, but
rule 1 takes priority
State assignment (4)

• The ‘good’ state assignment is now made by trying to

S1   000 - chosen for ease of initialisation
S2   001
S3   111 - other states chosen to satisfy rule 1
S4   011 - note that not all requirements can
S5   101   be satisfied, eg, S1 and S3

• Implementing this assignment (using D-types) requires 14
literals – compared with 19 for a simple binary assignment
• Better – not best?
State assignment (5)
• It is also possible to deliberately choose an
assignment which uses more than the minimum
number of flipflops in order to easily generate
outputs indicating a specific state (or states)
For example, ‘one-hot’ assignment

• Also remember to consider don’t-care and initial
(reset) states
Analysis of state machines
•   Sometimes we may need to ‘reverse engineer’ a
circuit – and derive a state diagram from a given
circuit

Procedure -
1. Determine the next-state and output functions
2. Construct the state table
3. Construct the state diagram (optional)
Analysis example (1)

• Fig 7-38
Analysis example (2)
• Determine Next state and Output functions
From diagram – Excitation equations
D0  Q0.EN  Q0.EN
D1  Q1.EN  Q1.Q0.EN  Q1.Q0.EN

Substituting Q*=D to get equations for state variables

Q0*  Q0.EN  Q0.EN
Q1*  Q1.EN  Q1.Q0.EN  Q1.Q0.EN
Analysis example (3)
Output equation -   MAX  Q0.Q1.EN

The state table can now be constructed by evaluating the
equations for every combination of state and input -
Analysis example (4)
State diagram -

• The design may now be modified and re-synthesised…

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