Introduction to CMOS Circuit Design by she20208

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									                            VLSI Circuit Design


                                       Chapter 1
 Intr oduction to CMOS Cir cuit Design

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Course Contents
           1. Introduction to CMOS Circuits
           2. MOS Transistor Theory
           3. CMOS Processing Technology
           4. Circuit Characterization Estimation
           5. CMOS Circuit and Logic Design
           6. CMOS Design Methods
           7. CMOS Testing
           8. CMOS Subsystem Design
           9. CMOS System Case study
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                                                                                 1
 Chapter 1: Introduction to CMOS Circuits

     • MOS Transistor Switches
     • CMOS Logic
     • Circuit and System Representations
     • CMOS Score Board




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MOS Transistor - nMOS
                             Gate          Conductor                    Poly
                    Drain                       Insulator                       Gate

                                                      Source

                                                                    D            S
                 n        n
            p-doped
            semiconductor substrate                            Diffusion

                                                      Gate
                    D                  D
                                           Drain                 Source
            G               G

                    S                  S           Substrate

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                                                                                                    2
MOS Transistor - pMOS
                             Gate          Conductor                          Poly
                    Drain                       Insulator                             Gate

                                                          Source

                                                                         D             S
                  p        p
             n-doped
             semiconductor substrate                                Diffusion

                                                          Gate
                     S                 S
                                               Drain                  Source
             G              G

                     D                 D               Substrate

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CMOS Switches - Basic
                                                                     Input           Output
                                                                        0            Good 0
         a          NSwitch            b   a                    b
                      s                                s=0
                                                                        1            Poor 1
         a                             b   a                    b
                                                       s=1
                      s

                                                                      Input          Output
                                                                        0            Poor 0
         a          PSwitch            b   a                    b
                                                       s=0
                      s
         a                             b                                1            Good 1
                                           a                    b
                      s                                s=1
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                                                                                                          3
CMOS Switches
                                                       s
                                                                                  s
         a         C - Switch          b   a                      b    a                  b
                                                                                  s
                       s                               s




                                                             5V
             Input              Output

               0                Good 0            5V                  0V

               1                Good 1
                                                       Vo = 5V-Vth         Vo=0V+Vth
                                                        Poor 1              Poor 0

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CMOS Logic - Inverter


             Vin                           Vout            1                          0




             Vin                           Vout

                                                             0                        1



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                                                                                                    4
CMOS Logic - Serial Structure
                    a              00    01   10    11

                                                              F               s1
          s1                                                          0            1
                                                                  0   OFF      OFF
          s2                                                 s2
                                                               1      OFF          ON
                    b

                    a               00   01   10        11
                                                              F               s1
                                                                      0            1
          s1
                                                                  0   ON       OFF
                                                             s2
          s2                                                   1      OFF      OFF
                    b
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CMOS Logic - Parallel Structure
            a
                               00        01        10        11           F             s1
                                                                                   0         1
s1                   s2                                                  0 OFF               ON
                                                                       s2
                                                                         1 ON                ON
            b
            a                  00        01        10        11
                                                                          F             s1
                                                                                   0         1
s1                   s2                                                   0        ON        ON
                                                                       s2
                                                                         1         ON    OFF
            b

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                                                                                                      5
CMOS Logic - NAND Gate




                                               (A+B)
                                                                   Y           A
                                                                           0       1
                                           Y
                                                                   0       1       1
                                       B                       B
                                                                   1       1       0
         A
                                                   (A&B)


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CMOS Logic - NOR Gate




                                               (A&B)

                                                           Y               A
                                                                       0       1
                                               Y
                                                               0       1       0
                                                           B
               A                        B
                                                               1       0       0

                                                   (A+B)

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                                                                                                 6
CMOS Logic - N-input Gates



                                                         N
                    B
         A                    N

                                                         B
                    A
                                                         A

                    B

                                                     A       N
                    N                                    B

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CMOS Logic - Complex Gates


                                                   A             B

                   Y = AB + CD
                                                    C            D
              A
              B                                                             Y
                                       Y
              C
              D                                    A             C

                                                    B            D



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                                                                                      7
CMOS Logic - Transmission Gate
                                       s
                                                                   s
                          a                    b         a              b
                                                                   s
                                       s


                   MUX 2-1                                        MUX 4-1
                              s                              S1    S1   S0     S0

              A                                     A

                      s                    Y        B
                                                                                              Y
              B                                     C

                              s                     D
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CMOS Logic - Latches

                              D                                         Q

                                   L

                                               Q


         D                                     Q             D                                    Q

         1                                                   0

                          Q                                             Q
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                                                                                                      8
CMOS Logic - D Flip-flop


                               Master                 Slave

          D                                                                 Q




          Clk



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CMOS Logic - Representation
     • Behavioral Representation
            – Functional, High level
            – For documentation, simulation, and verification
     • Structure Representation
            –   System Level - CPU, RAM, I/O
            –   Functional Level - ALU, Multiplier, Adders, ...
            –   Gate Level - AND, OR, NAND, NOR, XOR, ...
            –   Cricuit Level - Transistors, R, C, L.
            –   For design and simulation
     • Physical Representation
            – For fabrication


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                                                                                       9
CMOS Logic - Representation - Example

                     a                                 Behavioral :
                                            F
                     b                                          out = - (a&b)
                                                                out = (not(and a b))

                               Vdd                     Structural / Circuit:
                                                        part nand2 (a,b) -> out
                 a                            b         signal i1

                                            F                     Nfet   i1 a vss
                                                                  Nfet   out b i1
                      a                                           Pfet   out a vdd
                                   i1                             Pfet   out b vdd
                      b                                 end

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CMOS Logic - Representation - Example

                 Vdd                       Structural / Circuit / Spice :
                                           .SUBCKT NAND2 VDD VSS A B OUT
a                                  b       MN1 I1  A     VSS      VSS    NFET   W=8U L=4U …         ...
                                           MN2 OUT B     I1       VSS    NFET   W=8U L=4U …        ...
                                       F   MP1 OUT A     VDD      VDD    PFET   W=16U L=4U …        ...
         a                                 MP2 OUT B     VDD      VDD    PFET   W=16U L=4U …        ...
                                           CA A VSS      50fF
                                           CB B VSS      50fF
         b                                 COUT OUT      VSS       100fF

                                           .END



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                                                                                                          10
CMOS Logic - Representation - Example
                                    QBAR(Q)
                           A
         IN                                                  Q

         LD                                                           FLIP-FLOP :


         LDBAR(LD)                                  Structural / Gate :
                                                    Part flipflop (in, ld, ldbar, q, qbar)
                                                    signal a
                                                          tg (in, ld, ldbar) -> a
                                                          inv (a) -> qbar
                                                          inv (qbar) -> q
                                                          tg (q, ldbar, ld) -> a
                                                    End
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CMOS Logic - Representation - Physical
          Gate Electrode                    n-Diffusion
          Polysilicon                       Source and Drain                       pFET

           j+1
                                                    d
                      s    g        d                                 s   g   d
              j                                     g
                                                    s
           j-1

                    i-1     i       i+1             k
                                                    d          Gate Electrode
                                                               Polysilicon
                      s         g       d       g


                                                    s
                                        nFET
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                                                                                                           11
CMOS Logic - Representation - Physical
                         Inverter                            Transmission Gate
                                                                 SB

                                       Vdd            Vdd


                                       p-Transistor
                  In                               A                          B
                                           Out

                                       n-Transistor
          Polysilicon
                                       Metal
                                        Vss         Vss

                                                                 S
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CMOS Logic - Representation - Physical

                       Inverter                 Begin TG
                                                  t1: device n (2,1) or=east
                                   Vdd            t2: device p (2,5) or=east
                                                  wire alum (0,0) (4,0)
                                                  wire alum (0,6) (4,6)
                                   p-Transistor   wire poly (2,-1) (2,1)
             In                                   wire poly (2,7) (2,5)
                                      Out
                                                  wire alum (1,1) (1,5)
                                   n-Transistor   wire alum (3,1) (3,5)
Polysilicon                                       wire alum (0,3) (1,3)
                                   Metal
                                                  wire alum (3,3) (4,3)
                                    Vss
                                                  contact md (3,1)
                                                  contact md (3,5)
                                                End
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                                                                                               12
CMOS Logic - Representation - Gate

                                                  QBAR (Q)
                                           A
                         IN                                            Q

                       LD




     LDBAR (LD)


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CMOS Logic - Representation - Circuit

                                   LDBAR

                                                                 Vdd
                                        D
                                                          Q
                                                                            Q

                                                                 Vss

                                   LD
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                                                                                       13
CMOS Logic - Representation - Physical

                                       LDBAR


              Vdd



                                               D


                                                                 QBAR             Q




             Vss

                                       LD

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Scorecards
• Fully restored logic level, ie., output settles at Vdd or Vss.
• Transitin Times: Rise and fall times are of the same order.
• Memories are implemented both densely and with low
  power dissipation.
• Transmission gates pass both logic levels well.
• Power dissipation - almost zero static power dissipations.
• Precharging characteristics - both n-type and p-type devices
  are available for precharging a bus to Vdd and Vss.
• Power supply - voltage requires to switch a gate is a fixed
  percentage of Vdd.
• Packing density - requires 2n devices for n-inputs gates.
• Layout - CMOS encourages regular and easily automated
  layout styles.

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