Analog Circuit Design in Modern CMOS Technologies by she20208


									                            Seminar organized by
                  IEEE Singapore Solid-State Circuits Chapter
                      IC Design Centre of Excellence (ICDC)
                     Nanyang Technological University (NTU)
                         You are cordially invited to a seminar on

     Analog Circuit Design in Modern CMOS Technologies
SPEAKER:      Prof Bram Nauta
               University of Twente, The Netherlands
TIME/DATE: 10:00am - 11:00pm, 18 Dec 2009 (Friday)
VENUE:      Lecture Theatre 22 (SS2-B2-7)
            Nanyang Technological University (NTU), Singapore 639798
Location Map: click here for map

registration is needed. FOC.

Phase Locked Loops and AD converters are key circuits in modern integrated system design. Some
recent developments from the University of Twente are illustrated in this presentation.

A 2.2GHz 7.6mW Sub-Sampling PLL with −126dBc/Hz In-Band Phase Noise and 0.15psrms Jitter in
0.18μm CMOS.
[ISSCC 2009] This phase locked loop used a sampling phase detector in contrast to a conventional phase
detector. This way the in-band noise power of the PLL can significantly be reduced since it is not related
to the divider ratio N anymore. An order of magnitude in power is saved for comparable performance.

A 1.9 μW 4.4 fJ/Conversion-Step 10 bit 1 MS/s Charge-Redistribution ADC
[ISSCC2008] This AD converter achieves the best figure of merit ever published: 4.4 fJ/conversion. The
very-low power circuit only draws current when it does an actual conversion and several power saving
ideas have been implemented.

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