Behavioral Modeling of the Impact of Substrate Noise on

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Behavioral Modeling of the Impact of Substrate Noise on Powered By Docstoc
					Department of Electrical Engineering (ESAT)            MICAS


        Workshop on Substrate Noise in Mixed-Signal IC’s
               Leuven, September 5 – 6, 2001

            Behavioral Modeling
      of the Impact of Substrate Noise
          on Analog Circuit Design
      Yann Zinzius, Georges Gielen, Willy Sansen
               K.U.Leuven ESAT-MICAS, Belgium
                    yann.zinzius@esat.kuleuven.ac.be
                                              Overview
Department of Electrical Engineering (ESAT)       MICAS



l Introduction


l High-level modeling for analog design


l High-level modeling for analog design with
   substrate noise

l Conclusions
                                              Introduction (1)
Department of Electrical Engineering (ESAT)                    MICAS



      Package
      parasitics


     Substrate
     parasitics
                     1                             3



 1 Noise injection
 2 Noise transfer                                  Backside connection
 3 Noise impact                      2
                                                               Introduction (2)
Department of Electrical Engineering (ESAT)                                            MICAS
l Impact on analog design                               l Sensitive analog part
   m Bulk effect in the MOS                                m   Passive devices capacitively
     transistor                                                coupled with the substrate
     Vt = Vt0 + γ ⋅   (   2 ⋅ φ f + VSB − 2 ⋅ φ f   )      m
                                                           m
                                                               Weak signal of input stage
                                                               Single ended <-> differential
    gmb         γ                                       l Protection techniques
        =                 =χ                               m   Common-mode noise => fully
     gm 2 ⋅ 2 ⋅ φ f + VSB                                      differential design
          KP                                               m   Decoupling capacitance
             ⋅ (VGS − Vt )
                          2
     ID =                                                  m   Guard ring
           2
                                                           m   Phase shifting between digital
    m   Inductive effect due to bond                           clock and analog sampling
        wire of supplies
    m   Capacitive coupling between
        substrate and devices
        (junction or coupling
        capacitances)
                                              Overview
Department of Electrical Engineering (ESAT)       MICAS



l Introduction


l High-level modeling for analog design


l High-level modeling for analog design with
   substrate noise

l Conclusions
                                   High-Level Modeling
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                                               Functional level
l Different level of                            (Signal Flow Diagram)
   abstraction from the
   highest (functional level) to                Behavioral level
   the lowest (circuit level)                 (Equations, s-domain or z-
                                              domain functions and block
                                                  diagram, VHDLA)


l Use of the Behavioral level                       Macro level
   or Macro level                             (circuit with basic elements,
                                               controlled or not sources)

                                                    Circuit level
                                          (circuits with basic elements)
                                   Behavioral Modeling
Department of Electrical Engineering (ESAT)                      MICAS

l Apply the same input
   signal to the behavioral
                                              Behavioral
   model and the full circuit                   Model
                                                               Υ( ω)
                                                               Υ(jω)
   schematic                                                   y(t)
                                                           -
                                     u(t)                              e(t)
                                     U(jw)                             E(jw)
                                                           +
l Analysis of the difference                                v(t)
   signal between the outputs                     Actual
                                                  Model
                                                            V(jw)



l Use the “Least Squared
   Error” criterion :
                           æM                2ö
                        minç å {y (n) − v(n)} ÷
                           è n =1             ø
               Analysis of Integrated Systems
Department of Electrical Engineering (ESAT)   MICAS


      IMEC, K.U. Leuven and
     Ericsson test chip within
       BANDIT project work
    WLAN BASEBAND MODEM WITH
  IQ MODULATOR - IQ DEMODULATOR
   ANALOG-TO-DIGITAL CONVERTER
     TRACK-AND-HOLD AMPLIFIER
(220K GATE EQUIVALENT DIGITAL AREA,
    60 MHz-20 MHz GATED CLOCKS)




            8-bit ADC
                                                 Substrate Model
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                   Digital part                           Analog part


    Substrate
    network                           Epitaxial layer
Backside node
(equipotential)


                    Digital part                          Analog part
                  Behavioral Model                       Behavioral Model
                   or Macro Model                         (VHDL-AMS,
                       (VHDL)                               Equations)

 Backside node
                                     Current Injection
                                              Overview
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l Introduction


l High-level modeling for analog design


l High-level modeling for analog design with
   substrate noise

l Conclusions
                                    New Behavioral Model
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                                                 l Addition of an extra input
                                                   connected to vsub
                 Behavioral
                                  Υ(jω)
                                  Υ( ω)
                   Model
                                  y(t)
                                                 l Model the effect of vsub on
                              -
u(t)     x(t)                             e(t)
                                                   the output
U(jw)    X(jw)                            E(jw)
                              +                     m   reduced model complexity
                               v(t)
                   Actual
                               V(jw)                m   only sensitive parts included
                   Model


                                                 l Model the effect in time
                                                   domain, or using frequency
                                                   sweep
                                                      New Netlist
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l Generation of a new netlist
  m transistor-level netlist

  m substrate-model netlist
    extracted
l Multiple input system
  m “normal” inputs

  m substrate input              Vin    Transistor level circuit   Vout




                                              Substrate model

                              Vsub
                                              Backside node
                                                                           Design Flow
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                          Schematic
                                                                 l Simulation of the original
                        Original netlist
                                                                     netlist
                                                                 l   Generation of the layout
                       Simulations of the
   Input stimulis
                         original netlist                            (i.e. Layla)
                            Layout                               l   Generation of the
                       Substrate model
                                                                     substrate model (i.e.
                         extraction
                                                                     SubstrateStorm, Space)
                          New netlist
                                                                 l   New netlist generation
 Input and substrate
    noise stimulis
                       Simulations of the
                          new netlist
                                                                 l   Simulation of the new
                       Behavioral model     Comparaison of the
                                                                     netlist
                                                                     Generation of the model
                         development        simulations output
                                                                 l
                                                                     Verify the model
 Input and substrate   Simulations of the
    noise stimulis     behavioral model                          l
                       Example : 8-bit ADC layout
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                             8-bit ADC
                                  Simulation Setup pr1
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l VSUB sinusoidal input
   signal

l IN+ & IN- ramp from 1 V to
   2.6 V                             IN +            OUT +

                                     IN -            OUT -
l Simulator ELDO
                                              VSUB
                                              Simulation pr1
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 l Simulation with and
   without noise source
 l Oscillation on top of
   the signal
 l Non-constant
   amplitude of the
   oscillations ?
                                        Time Analysis pr1
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l Dependence on input
   voltage value
   Þ transistor operating
   point
                                                  Model integration
Department of Electrical Engineering (ESAT)                             MICAS

                  Original                Out_m
                  Netlist
                                          Out_p


                             Substrate
                             Behavioral
                               Model


Vin_m     Vin_p                     Vnoise



                                          From simulations
                                            Þ possibility to provide direct
                                               noise signal to the output
                                             Þ substrate model behavior
          Application : 2nd Bandit test chip
Department of Electrical Engineering (ESAT)                    MICAS


                                  Test chip in AµE 0.35µm CMOS 3.3V
                                   Low-noise IQ demodulator circuits
                               BANDIT
                                    with embedded comparators and
                                CHIP          noise sensors




                                         Comparators with
                                         different noise reduction
                                         measures to be tested
             Test chip part of Bandit project
      Project partners K.U.Leuven, IMEC, Ericsson
                                              Conclusions
Department of Electrical Engineering (ESAT)               MICAS



l Introduction of a possible approach to generate high-level
   models for substrate noise impact on analog designs

l Description of substrate noise behavior on the output


l On-going work :
   The analysis still needs to be improved and compared to
   measurements